1. Homework #5 + solution

2. Question 1: Convert to DLX assembly (Assume that variables i, k correspond to registers 19 20, and that the array save starts at address Sstart) while (save[i]==save[k-i]) i = i+1;

3. Solution Address of save[0] = Sstart addir4r0Sstart addr1r4r19 subr2r20r19 addr3r4r2 lwr5r10 lwr6r30 xorr7r5r6 bnezr72 addir19r191 beqzr0-9 while ( save[i] == save[k-i] ) i=i+1;

4. Question 2: Consider the ALU environment in the DLX datapath. (a) List the tasks performed by the ALU in every control state. (b) List the control signals that are input to the ALU by the control. (c) Bonus: Implement the ALU environment.

5. ALU: Tasks performed in the control states OperationState addDecode op, op=add/sub/and/or/xor. Alu addAluI rel, rel=lt, eq, gt, le, ge, ne. TestI addAdr. Comp. addB.Taken addJR addSavePC addJALR

6. ALU: Control Signals Signals that control the functionality of the ALU: ALUF[2:0] add (active during states: Decode, AluI, Adr.Comp., B.Taken,SavePC, JR, JALR). test (active during states: TestI). ALUF[2:0] – arithmetic / logical ALU operations 011add 010sub 110and 101or 100xor ALUF[2:0] – test conditions 001gt 010eq 011ge 100lt 101ne 110le IR[2:0] = func[2:0] IR[28:26] = opcode[2:0]

7. MUX(32) OR(32) AND(32) XOR(32) MUX(32) Comparator(32) OR INV MUX(32) ALU: Implementation Next slide

8. ZERO(32) AND INV AND INV OR AND OR ALU: Implementation (cont’) Comparator

9. Question 3: Consider all the instructions of the DLX. Register B in the datapath is loaded during the Decode state without taking into consideration the current instruction. (a) Specify the instructions in which register B must be loaded. (b) Explain why the functionality is correct if register B is loaded also during instructions in which it need not be loaded. (c) Can you explain the decision to always load register B.

10. “Register B” The instructions in which register B is loaded: add sub and or xor store Register B is not involved in computations during instructions in which it need not be loaded. Therefore, functionality is correct. Loading register B always (during Decode state), shortens the length of the path in the Control State Machine when executing instructions that need register B loaded.

11. Consider the execution of the i th instruction: The IR register outputs the i th instruction from the beginning of the Decode state (of the i th instruction) till the end of the first clock cycle in the Fetch state (of the i+1 st instruction). Therefore, the address of the register which is loaded into register B is not changed during the execution of the i th instruction. Register B content is relevant only for R-type instructions (and Store inst.). Therefore, we may consider the address of the register which is loaded into register B, as. We refer only to R-type instructions. “Register B” – Setting ce=1 or Removing The functionality of the DLX is not damaged due to (1) setting always Bce=1, or (2) Removing register B.

12. Two cases may damage the functionality: 1.The content of RS2 is changed. May happen only during WBR state in which the output of reg. B (the content of RS2) is irrelevant anymore. Therefore, functionality is not damaged. 2. The GPR Env. doesn’t output the content of RS2. May happen only during a write operation to the GPR - Only during WBR state in which the output of reg. B (the content of RS2) is irrelevant anymore. Therefore, functionality is not damaged. Register B is necessary for minimizing the clock period. We may conclude: If (1) RS2 is not changed, and (2) The GPR Env. outputs the content of RS2, Then, Register B outputs the content of RS2 (=RS2 @ beginning of the i th instruction ).