1. SOAR Processing with Field Programmable Gate Arrays Presented by Matthew Scarpino Hoplite Systems LLC

2. Introduction Technical focus: applications of reconfigurable computing Technical focus: applications of reconfigurable computing Selected for initial funding by DARPA Selected for initial funding by DARPA “Cognitive Processing Hardware Elements” “Cognitive Processing Hardware Elements” RAISE – Reconfigurable Architecture for Improved Soar Execution RAISE – Reconfigurable Architecture for Improved Soar Execution

3. What is Reconfigurable Computing? Altering architecture and content to meet the behavioral requirements Altering architecture and content to meet the behavioral requirements CPU CPU Changing content, fixed architecture Changing content, fixed architecture Optimized for general-purpose applications Optimized for general-purpose applications FPGA FPGA Content/architecture dynamically configurable Content/architecture dynamically configurable Can be optimized for a specific application Can be optimized for a specific application

4. Virtex-II FPGA Structure FG 4 4 MEM FF CARRYCARRY

5. Virtex-II FPGA Structure

6. Virtex-II Configuration Similar to compilation/assembly in CPU Similar to compilation/assembly in CPU Sends a bitstream into the FPGA Sends a bitstream into the FPGA Traditional process: Traditional process: Verilog, VHDL Verilog, VHDL Hardware design synthesized into netlist Hardware design synthesized into netlist Netlist implemented onto specific device Netlist implemented onto specific device

7. Virtex-II Configuration Non-traditional: Low-level design Non-traditional: Low-level design Configure each FPGA resource separately Configure each FPGA resource separately Used for designs with repeated structures Used for designs with repeated structures Allows for partial reconfiguration Allows for partial reconfiguration Configure individual columns of an FPGA Configure individual columns of an FPGA Vital for reconfigurable computing Vital for reconfigurable computing

8. Challenge of Embedded Soar: Rete WMEs ALPHA1 TOP NODE JOIN BETA ALPHA2 ALPHA3 ALPHA4 BETA JOIN BETA JOIN PRODUCTIONS JOIN

9. Challenge of Embedded Soar: Rete Structure depends on production rules Structure depends on production rules Net re-arranges with changing conditions Net re-arranges with changing conditions Requirement: Dynamic Memory Allocation Requirement: Dynamic Memory Allocation Needed for linked-lists, pointers Needed for linked-lists, pointers Interacts with Memory Management Unit Interacts with Memory Management Unit Difficult on an embedded, distributed system Difficult on an embedded, distributed system

10. RAISE Structure Dynamic memory allocation is not an option Dynamic memory allocation is not an option FPGAs and OS-less embedded processors FPGAs and OS-less embedded processors Fixed amount of memory for each object Fixed amount of memory for each object Advance knowledge of object attributes Advance knowledge of object attributes Determined by input or goal context experience Determined by input or goal context experience Each attribute stored in particular order Each attribute stored in particular order Each attribute takes a single value Each attribute takes a single value

11. RAISE Structure Object Memory Switching Logic Production Output WMEs Operators

12. RAISE Structure Simplification and CompressionSimplification and Compression Keep memory requirements to a minimumKeep memory requirements to a minimum Remove unnecessary data structuresRemove unnecessary data structures Examples: WMEs and PreferencesExamples: WMEs and Preferences Scalability Scalability Concurrent FPGA processingConcurrent FPGA processing Greater efficiency than SMPGreater efficiency than SMP Division of laborDivision of labor

13. RAISE Structure FPGA FPGA Contains object memory (WMEs) Contains object memory (WMEs) Performs combinational logic Performs combinational logic Configuration Device Configuration Device Activates operators Activates operators Configures FPGA Configures FPGA FPGA Configuration Device (CD)

14. RAISE Operation PERCEPTION/ SYMBOL GENERATION ALPHA MEMORY BUFFER CONFIGURATION DEVICE ACTUATION/ CONTROL FPGA

15. Conclusion Design still in planning stage Design still in planning stage Will evolve as work progresses Will evolve as work progresses Structural analogue for cognitive processing Structural analogue for cognitive processing Distributed memory and processing Distributed memory and processing Combination of small computational elements Combination of small computational elements Behavior controls structure Behavior controls structure