1. xxx Miguel Urteaga A Ph. D. thesis proposal, July 16 th, 2002

2. Outline Motivation Research to Date Proposed Research Demonstration of high-bandwidth manufacturable InP mesa-HBTs Circuit demonstrations in technology

3. Motivation

4. Why do we want fast transistors? Fiber Optic Communication Systems 40 Gb/s, 160 Gb/s(?) long haul links mm-Wave Wireless Transmission high bandwidth communication links, atmospheric sensing, automotive radar Military Electronics Applications > 100 GHz mixed-signal ICs for digital microwave radar

5. InP vs Si/SiGe HBTs InP system has inherent material advantages over Si/SiGe 20x lower base sheet resistance, 5 x higher electron velocity, 4x higher breakdown-at same f t. but… Current generation production Si/SiGe HBTs are almost as fast as InP counterparts due to 5x smaller scaling and… SiGe HBTs offer much higher levels of integration due to underlying Si platform

6. Reduce vertical dimensions to decrease transit times Reduce lateral dimensions to decrease RC time constants Increase current density to decrease charging resistances For a x 2 improvement of all parasitics: f t, f max, logic speed... base  2: 1 thinner collector 2:1 thinner emitter, collector junctions 4:1 narrower current density 4:1 higher emitter Ohmic, collector Ohmic 4:1 less resistive Scaling Laws for HBTs

7. Which technology is built to scale? E C B InP mesa-HBT before passivationCross-section of SiGe HBT Narrow emitter: 0.18 um Self-aligned regrown emitter High current density: 10 mA/um 2 SiO2 trenches: small collector capacitance Planar device : high yield Wide emitter: >1 um Self-aligned base metal liftoff: low yield Low current density: 2 mA/um 2 Parasitic base collector capacitance under base contacts Non-planar device : low yield

8. Scaling of collector-base junction High yield self-aligned base-emitter junction formation Improving emitter Ohmic contacts Heat flow for high current-density operation Device passivation for long-term reliability Planar process flow for high levels of integration Key Challenges for InP HBTs

9. Revolutionary Approach: Si like InP HBT *monocrystalline where grown on semiconductor polycrystalline where grown on silicon nitride Objectives: Extreme parasitic reduction: speed Fully planar device: yield Silicon-like structure: yield Approach: Implanted isolated subcollector planar surface: yield Pedestal collector, regrown base submicron collector scaling: speed small collector junction: speed thick extrinsic base: speed planar base-collector junction: yield Regrown submicron emitter submicron emitter scaling: speed no submicron etching: yield no emitter-base liftoff: yield large emitter contact: low R ex, speed large emitter contact: yield Approach currently being pursued by D. Scott and N. Parthasarathy at UCSB

10. Evolutionary Approach: Optimized InP mesa-HBT S.I.Substrate N+ subcollector N- collector Emitter contact Si 3 N 4 Sidewall Base contact SiO 2 sidewall Si 3 N 4 Sidewall Base layer Collector contact Objectives: Improve speed, yield, and integration density of mesa-HBT technology Contribute processes for development of Si-like technology Approach: Dielectric sidewall processes self-aligned base-emitter junction with improved yield: no liftoff self-aligned definition of base Ohmic contact width for minimum C bc Ion implantation for base pad isolation Extrinsic C bc reduction Optimize Ohmic contact metallurgies R ex reduction essential for high-speed logic Skip lateral scaling generation with improved base Ohmics Planar View Collector contact Emitter contact Base contact Ion Implant Region Base contact Sidewall

11. Research to Date

12. Submicron transferred-substrate HBTs with electron-beam defined emitter and collector contacts Device measurement and characterization to 220 GHz G-band (140-220 GHz) small-signal amplifier designs Submicron HBTs by Substrate Transfer

13. Submicron HBTs have very low C cb (< 5 fF) Small reverse transmission characteristics and small output conductance make accurate device measurements difficult UCSB measurement set-up allows device measurements to 220 GHz Accurate on-wafer calibration is essential LRL calibration with correction for Line standard complex characteristic impedance First reported transistor measurements in 140-220 GHz band 2001 DRC, Notre Dame, IN On-wafer Device Measurements Transistor Embedded in LRL Test Structure 230  m UCSB 140-220 GHz VNA Measurement Set-up

14. Emitter: 0.3 x 18  m 2, Collector: 0.7 x 18.6  m 2 I c = 5 mA, V ce = 1.1 V Transferred-Substrate Device Results unbounded U Recent device measurements show singularity in Unilateral Power Gain due to small negative output conductance Not predicted from hybrid-  transistor model Cannot extrapolate f max from device measurements Effect may arise from second- order transport effects in collector space charge region Ccb cancellation weak IMPATT effects “Power gain singularities in Transferred-substrate InP/InGaAs-HBTs,” submitted to IEEE TED

15. Applications:  Wideband communication systems  Atmospheric sensing  Automotive radar Utilize high available gain of submicron transferred substrate HBTs for tuned small-signal amplifiers in 140-220 GHz band State-of-the-art InP-based HEMT Amplifiers with submicron gate lengths  3-stage amplifier with 30 dB gain at 140 GHz. Pobanz et. al., IEEE JSSC, Vol. 34, No. 9, Sept. 1999.  3-stage amplifier with 12-15 dB gain from 160-190 GHz Lai et. al., 2000 IEDM, San Francisco, CA.  6-stage amplifier with 20  6 dB from 150-215 GHz. Weinreb et. al., IEEE MGWL, Vol. 9, No. 7, Sept. 1999. Ultra-high Frequency Amplifiers (140-220 GHz)

16. First Generation: Single-Stage Amplifier S21 Measured 6.3 dB peak gain at 175 GHz Gain per-stage amongst highest reported Common-emitter design with microstrip matching network Device dimensions:  Emitter area: 0.4 x 6  m 2  Collector area: 0.7 x 6.4  m 2 Presented at 2001 GaAsIC Conference Cell Dimensions: 690  m x 350  m

17. Second Generation: Multi-Stage Amplifiers Three-stage amplifier designs:  12.0 dB gain at 170 GHz  8.5 dB gain at 195 GHz Cascaded 50  stages with interstage blocking capacitors To be presented 2002 GaAsIC conference Cell Dimensions:1.6 mm x 0.59 mm

18. Technological Implementation

19. Evolutionary Approach: Optimized InP mesa-HBT S.I.Substrate N+ subcollector N- collector Emitter contact Si 3 N 4 Sidewall Base contact SiO 2 sidewall Si 3 N 4 Sidewall Base layer Collector contact Objectives: Improve speed, yield, and integration density of mesa-HBT technology Contribute processes for development of Si-like technology Approach: Dielectric sidewall processes self-aligned base-emitter junction with improved yield: no liftoff self-aligned definition of base Ohmic contact width for minimum C cb Ion implantation for base pad isolation Extrinsic C cb reduction Optimize Ohmic contact metallurgies R ex reduction essential for high-speed logic Skip lateral scaling generation with improved base Ohmics Planar View Collector contact Emitter contact Base contact Ion Implant Region Base contact Sidewall

20. Optimized Ohmic contacts Self-aligned base-emitter junction formation Self-aligned base Ohmic width definition Ion Implantation for base-pad capacitance reduction Technological Implementation

21. Optimized Ohmic contacts are essential for realization of high performance mesa-HBTs Currently UCSB has the world’s best base Ohmic contacts and the world’s worst emitter Ohmic contacts Collector contacts have not been closely examined because of Schottky collector contact TS-HBTs and the use of thick InGaAs sub-collector layers InP HBT Ohmic Contacts

22. Base Ohmic Contacts Base Ohmic process developed by M. Dahlstrom has reduced specific contact resistivity of p-type contacts to < 10 -7  cm 2 Improvement seen for C and Be doped samples Transfer length of < 0.1  m allows aggressive scaling of base Ohmic contact width for reduced C cb Process UV Ozone treatment of InGaAs surface NH 4 OH oxide strip Pd/Ti/Pd/Au metallization Proposed Research Incorporate process with new self- aligned base-emitter junction processes Investigate thermal stability of contacts

23. Emitter Ohmic Contacts UCSB InP HBTs have large extrinsic emitter resistance R ex Emitter resistance has contributions from vertical contact resistance, and resistances of semi-conductor layers. Approximate as R ex =  e /A e UCSB:  e = 30-50  m 2 NTT:  e = 7  m 2 M. Ida et. al. 2001 IEDM Variability of UCSB contacts suggest processing related problems Proposed Research Optimize Ohmic contacts to n-InGaAs using refractory metallization if possible Determine source of high emitter resistance and optimize epi-layers and/or process to reduce R ex

24. Collector Ohmic Contacts Proposed Research Optimize Ohmic contacts to n-InP Investigate use of alloyed contacts (i.e. AuGe, Pd/Ge) S.I.Substrate N+ subcollector N- collector W mesa W c,gap In typical mesa-HBT, extrinsic collector resistance R c is much smaller than R ex but… Subcollector thickness should be minimized for device planarity, and for base-pad capacitance isolation implant, T subcollector < 1500 Ang and, InGaAs should be eliminated from subcollector for thermal considerations Collector contacts should be made to thin InP subcollector regions and R c will be comparable to R ex

25. Base-Emitter Junction Formation Current UCSB base-emitter junction formation relies on undercut of emitter semiconductor and self-aligned liftoff of thin base metal Acceptable process for high-performance, small-scale integration, research fabrication Unacceptable process for high-performance, large-scale integration, production fabrication

26. Base-Emitter Junction Formation Current Base-Emitter ProcessFailure Mechanisms

27. Utilize isotropic deposition of CVD dielectric films and anisotropic etch rates of RIE to form sidewall spacers Dielectric Sidewall Formation Emitter Contact/ Mesa formationCVD Dielectric film Reactive Ion EtchSidewall Formation

28. Dielectric sidewall process has been developed at UCSB Utilize dry-etched tungsten emitter contacts for improved emitter profile and sidewall formation Key challenges Etch damage to base semiconductor Passivation of InP/InGaAs surfaces with dielectrics Scaling sidewall thickness Hydrogen passivation of carbon doped InGaAs base Dielectric Sidewall Formation: Current Status 1  m Tungsten Emitter w/ 1000A SiN sidewall

29. Carbon is preferred to Beryllium as base dopant because of lower diffusion coefficient and higher solubility Hydrogen passivation of Carbon acceptors in InGaAs is observed in MOCVD growth and during Methane base dry-etches Si x N y CVD deposition utilizes SiH 4 carrier gas. Carbon passivation during ECR-CVD of Si x N y has been reported. Ren, F et. al. Solid-State Electronics May, 1996 Possible Solutions Si x N y deposition on base-emitter grade Anneal out hydrogen; 400 C ~10 min anneal requires refractory contacts Use Be doped base GaAsSb base layer Key Challenge: Hydrogen Passivation of C-doped InGaAs

30. InAlAs/GaAsSb/InP DHBTs In 52 Al 48 As GaAs 50 Sb 50 InP MOCVD of C-doped GaAsSb shows no hydrogen passivation Initial experiments at UCSB show no passivation after Si x N y deposition High performance InP/GaAsSb/InP DHBTs have been demonstrated f t, f max = 300 GHz Dvorak, et. al. IEEE EDL Aug. 2001 InAlAs/GaAsSb/InP HBTs have favorable band lineup and good surface properties for BE passivation MBE growth of p-type GaAsSb looks promising Be : N A = 6.6E19 cm -3 ;  = 26.6 cm 2 /Vs C : N A = 4E19 cm -3 ;  = 46 cm 2 /Vs Large area DC I-V

31. Approaches to base-emitter junction formation with sidewall spacers Blanket metallization and planarization etch back Selective metallization of base semiconductor: CVD, or electroplating Self-aligned liftoff of thin base metal with sidewalls to prevent metal-to-metal short circuits Self-aligned base-emitter junction formation

32. Base-emitter junction formation: Base metal liftoff Self-aligned emitter mesaSidewall formationThin metal liftoff

33. Base-emitter junction formation: Selective metallization Sidewall FormationSelective CVD Tungsten ??? Sidewall FormationThin seed metalElectroplate CVD Electroplate

34. Base-emitter junction formation: Planarization etchback Sidewall FormationBlanket metallizationPlanarization EtchbackMetal sidewall removalStrip planarization material

35. Planarization etchback experiments Similar process is incorporated in Hitachi GaAs HBT process Reference Planarization etch back experiments at UCSB were unsuccessful due to non- uniformity of RIE system Experiments at Rockwell Science Center look better but still work to be done Etch selectivity between planarization material and Tungsten is a key processing issue Proposed Research Further experiments at RSC to determine feasibility of process If unsuccessful, look at alternative self- aligned processes

36. Base Ohmic transfer length < 0.1  m allows for aggressive scaling of base Ohmic contacts for reduced C bc Current self-aligned liftoff process requires accurate stepper alignment and emitter topology presents challenges for further scaling Low yield seen for 0.3  m base Ohmic width Utilize sidewall process for base Ohmic definition Self-aligned base Ohmic formation

37. Self-aligned base Ohmic: Process Flow Outer sidewall formation RIE base metal Self-aligned metallization Self-aligned base Ohmic Sidewall thickness determined by thickness of PECVD deposition Repeatable definition of base Ohmic width if base metal can be selectively dry etched Continue process with self- aligned base-mesa etch Goal: Repeatable, high-yield definition of < 0.3  m base metal width

38. Base contact pad represents considerable fraction of total extrinsic base collector capacitance ~34 % of total C cb for current generation ECL logic transistors with 0.7  m emitter and 0.5  m base Ohmic width operating at 2.5 x 10 5 A/cm 2 Fraction of total C cb will increase dramatically as devices are laterally scaled for reduced C cb and vertically scaled for high current density operation ~52 % of total C cb, for next generation ECL logic transistors with 0.5  m emitter and 0.3  m base Ohmic width operating at 5 x 10 5 A/cm 2 Base-pad Capacitance Planar View Collector contact Emitter contact Base contact pad Base contact

39. Approaches to reducing extrinsic base pad capacitance include: Lateral undercut of contact region for isolation Dielectric refill and planarization of extrinsic region Ion implantation of extrinsic base region Ion Implantation of InP Damage implants of light ions in InP tend to generate shallow level traps Unsuitable for device isolation Adequate for base-pad capacitance reduction Base-pad capacitance reduction

40. Base-pad capacitance reduction: He + Implant Circuit simulations show sheet resistance > 1M  square is adequate to provide base-pad isolation Implant experiments with He + into 1500 Ang. InP sub-collector show sheet resistance of ~ 10 M  square Projected range of He + implant will allow implant as first processing step Proposed Research Transistor fabrication with base-pad isolation implant Determine minimum implant to device separation Explore Fe implant for device isolation pending experiments by N. Parthasarathy Implant Region Planar View Cross-section

41. InGaAs 1E19 Si 300 Å Grade 1E19 Si 200 Å InAlAs 8E17 Si 300 Å Grade 8E17 Si 233 Å Grade 2E18 Be 67 Å InGaAs 8E19 C 300 Å Grade 1E16 Si 200 Å InP 2E18 Si 1100 Å InGaAs 1E19 Si 50 Å Layer Structure for Advanced mesa-HBT InAs 2E19 Si 200 Å InGaAs 1E16 Si 200 Å Emitter cap, InAs for improved contact resistance Thin InAlAs emitter GaAsSb or Be-doped if necessary Collector setback layer 1500 Ang. total collector thickness InP 1E19 Si 1500 Å Thin subcollector etch stop Subcollector; no buffer layer

42. Predicted Performance

43. State-of-the-art InP mesa-HBTs NTT: f t = 341 GHz, f max = 250 GHz 1500 Ang. collector, high current density 8 x 10 5 A/cm 2, lateral undercut for base pad isolation M. Ida et. al. 2001 IEDM SFU: f t = 300 GHz, f max = 300 GHz GaAsSb base, 2000 Ang. collector, airbridge contacts for base pad isolation, lateral etch collector undercut M. Dvorak, et. al. IEEE EDL Aug. 2001 UCSB: f t = 280 GHz, f max >450GHz Graded C-doped InGaAs base, 2000 Ang. composite collector, highly- scaled base Ohmics, no base pad isolation M. Dahlstrom, et. al. 2002 IPRM UCSB record f max mesa-HBT Figures-of-merit do not tell the whole story

44. Mesa-HBTs for Digital Logic Transistor figures-of-merit do not accurately predict digital logic speed Time constants C cb  V logic /I c and C cb R ex have larger contribution to digital logic gate delays than to f t UCSB record 87 GHz static frequency divider fabricated with f t = 200 GHz, f max = 180 GHz device operating at J e = 2.5 x 10 5 A/cm 2 PK Sundararajan PhD thesis Similarly, MSG/MAG is better metric for mm-wave tuned amplifier design than Unilateral power gain used to extrpolate f max

45. Use HBT SPICE model to predict improvements in device performance from process enhancements Next generation ECL transistor: W e = 0.5  m, L e = 3.0  m, J e = 5 x 10 5 A/cm 2, T collector = 1500 Ang, T base = 300 Ang Physical parameters from current generation mesa-HBTs Consider improvements in f t and f max Maximum ECL static divider frequency (no layout parasitics) Maximum available gain at 175 GHz ( L e = 6  m) Predicted Performance: SPICE Simulations

46. Predicted Performance: R ex Reduction Base Ohmic width = 0.5  m, Standard base-pad capacitance  e (  -  m 2 ) ftft f max Max Divider Freq. MAG @ 175 GHz 50233 GHz423 GHz64 GHz4.9 dB 40248 GHz434 GHz81 GHz5.0 dB 30266 GHz446 GHz92 GHz5.1 dB 20287 GHz458 GHz102 GHz5.3 dB 10313 GHz472 GHz117 GHz5.6 dB 5329 GHz478 GHz121 GHz5.8 dB

47. Predicted Performance: Self-aligned base Ohmic  e = 30  -  m 2, Standard base-pad capacitance Base Ohmic Width ftft f max Max. Divider Freq. MAG @ 175 GHz 0.5  m 266 GHz446 GHz92 GHz5.1 dB 0.25  m 290 GHz464 GHz109 GHz6.0 dB

48. Predicted Performance: Base-pad Isolation  e = 30  -  m 2, Base Ohmic width = 0.5  m Base Pad Isolation ftft f max Max. Divider Freq. MAG @ 175 GHz No266 GHz446 GHz92 GHz5.1 dB Yes289 GHz450 GHz112 GHz5.7 dB

49. Predicted Performance: All Enhancements  e = 10  -  m 2, Base Ohmic width = 0.25  m, Base-pad Isolation ftft f max Max. Divider Freq. MAG @ 175 GHz 344 GHz487 GHz160 GHz7.2 dB 8.8 dB with  b_cont = 1 x 10 -8  -cm 2

50. Proposed Circuit Demonstrations Static Frequency Dividers: divide-by-two, divide-by-four Analog Wideband Amplifiers: Cherry-Hooper mm-Wave Tuned Amplifiers: 140-220 GHz frequency band

51. Research Timeline Implement process enhancements using current device mask set Base pad isolation:

52. Things to do when: SEM Rockwell experiments More samples for S3 processing at Rockwell: Thicker emitter, thinner base metal (how thin?) Emitter contact experiments on remaining InGaAs wafer Literature search on N+ InGaAs contacts ---Work function stuff???? Something besides Ti Mask set for Ion Implant of InP DHBTs for base pad reduction Implant through whole structure or just base collector?? Measure straggle on bits an pieces of He implanted structure Layer structures from Dennis InAs cap on InAlAs for Ohmic contact studies InAlAs grade on carbon doped InGaAs. Check for H passivation maybe able to use old mattias Epi, also for implant stuff. GaAsSb when system B comes back up!! Order IQE epi. Go See Val tomorrow!!!