1. CSCI 320 Computer Architecture Chapter 5 Large and Fast: Exploiting Memory Hierarchy

2. Memory Technology  Static RAM (SRAM) l 0.5ns – 2.5ns, $2000 – $5000 per GB  Dynamic RAM (DRAM) l 50ns – 70ns, $20 – $75 per GB  Magnetic disk l 5ms – 20ms, $0.20 – $2 per GB  Ideal memory—large, fast, cheap l Access time of SRAM l Capacity and cost/GB of disk §5.1 Introduction 100:1 1:100 speed cost

3. The Memory Hierarchy: Why Does it Work?  Principle of Locality —Study shows that Programs access a small proportion of their address space at any time  Temporal Locality (Locality in Time): Items accessed recently are likely to be accessed again soon Examples: loop code, sorting an array  Spatial Locality (Locality in Space): Items near those accessed recently are likely to be accessed soon Examples: execution of sequential instructions, access to an array, execution of a procedure

4. Locality In A Memory-Reference Pattern Execution time Memory address

5. The Memory Hierarchy Increasing distance from the processor in access time L1$ L2$ Main Memory Secondary Memory Processor (Relative) size of the memory at each level Inclusive– what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM 4-8 bytes (word) 1 to 4 blocks 1,024+ bytes (disk sector = page) 8-32 bytes (block)  Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology

6. Speed(ns):0.5ns2ns6ns 100ns 10,000,000ns Size (MB):0.00050.051-4 100-1000100,000 Cost ($/MB): ---$100$30 $1 $0.05 Technology:Flip-flopsSRAMSRAM DRAMDisk Control Data path Processor Regs Secon- dary Mem- ory L2 Cache L1 Main Mem- ory Another view of The Memory Hierarchy

7. The Memory Hierarchy: Terminology  Hit: data is in some block in the upper level (Block X) l Hit Rate: the fraction of memory accesses found in the upper level l Hit Time: Time to access the upper level which consists of RAM access time + Time to determine hit/miss  Miss: data is not in the upper level so needs to be retrieve from a block in the lower level (Block Y) l Miss Rate = 1 - (Hit Rate) l Miss Penalty: Time to replace a block in the upper level + Time to deliver the block the processor l Hit Time << Miss Penalty Lower Level Memory Upper Level Memory To Processor From Processor Block X Block Y

8. How is the Hierarchy Managed?  registers  memory l by compiler (programmer?)  cache  main memory l by the cache controller hardware  main memory  disks l by the operating system (virtual memory) l virtual to physical address mapping assisted by the hardware (TLB) l by the programmer (files)—reading and storing files

9. MIPS R1000 Processor die

10.  Two questions to answer (in hardware): l Q1: How do we know if a data item is in the cache? l Q2: If it is, how do we find it? l 3 organizations: Direct mapped, Set associative, Fully associative Cache memory

11. 3 ways to organize cache memory  Direct mapped For each item of data at the lower level, there is exactly one location in the cache where it might be - so lots of items at the lower level must share locations in the upper level  Address mapping: (block address) modulo (# of blocks in the cache)  Let’s first consider block sizes of one word

12. Caching: A Simple Example—Direct mapped 00 01 10 11 Cache Main Memory Q2: How do we find it? Use next 2 low order memory address bits – the index – to determine which cache block (i.e., modulo the number of blocks in the cache)— called “tag” field TagData Q1: Is it there? Compare the cache tag to the high order 2 memory address bits to tell if the memory block is in the cache Valid 0000xx 0001xx 0010xx 0011xx 0100xx 0101xx 0110xx 0111xx 1000xx 1001xx 1010xx 1011xx 1100xx 1101xx 1110xx 1111xx Two low order bits define the byte in the word (32b words)— byte addressable memory (block address) modulo (# of blocks in the cache) Index

13. Direct Mapped Cache 0123 4 3415  Consider the main memory word reference string 0 1 2 3 4 3 4 14 Start with an empty cache - all blocks initially marked as not valid

14. Direct Mapped Cache 0123 4 3415  Consider the main memory word reference string 0 1 2 3 4 3 4 15 00 Mem(0) 00 Mem(1) 00 Mem(0) 00 Mem(1) 00 Mem(2) miss hit 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 014 11 15 00 Mem(1) 00 Mem(2) 00 Mem(3) Start with an empty cache - all blocks initially marked as not valid l 8 requests, 6 misses tag

15.  One word/block, cache size = 1K words MIPS Direct Mapped Cache Example 31 30... 13 12 11... 2 1 0 Byte offset 20 Tag 10 Index Data IndexTagValid 0 1 2. 1021 1022 1023 20 Data 32 Hit

16. Example: Larger Block Size  64 blocks, 16 bytes/block l To what block number does address 1200 map into?  Block address =  1200/16  = 75  Block number = 75 modulo 64 = 11 TagIndexOffset 03491031 4 bits6 bits22 bits Block number Byte number

17.  Read hits (I$ and D$) l this is what we want!  Write hits (D$ only)—two ways to update lower level l Write-back--allow cache and memory to be inconsistent -write the data only into the cache block (write-back the cache contents to the next level in the memory hierarchy when that cache block is “evicted”) -need a dirty bit for each data cache block to tell if it needs to be written back to memory when it is evicted l Write-through--require the cache and memory to be consistent -always write the data into both the cache block and the next level in the memory hierarchy (write-through) so don’t need a dirty bit -writes run at the speed of the next level in the memory hierarchy – so, slow! – or can use a write buffer, so only have to stall if the write buffer is full Handling Cache Hits TagIndexOffset 03491031 4 bits6 bits22 bits

18. Write Buffer for Write-Through Caching  Write buffer between the cache and main memory l Processor: writes data into the cache and the write buffer l Memory controller: writes contents of the write buffer to memory  The write buffer is just a FIFO(First In First Out) l Typical number of entries: 4 l Works fine if store frequency (w.r.t. time) << 1 / DRAM write cycle  Memory system designer’s nightmare l When the store frequency (w.r.t. time) → 1 / DRAM write cycle leading to write buffer saturation -One solution is to use a write-back cache; another is to use an L2 cache Processor Cache write buffer DRAM with respect to

19. Cache Misses  On cache hit, CPU proceeds normally  On cache miss l Stall the CPU pipeline l Fetch block from next level of hierarchy l Instruction cache miss -Restart instruction fetch after above two steps l Data cache miss -Complete data access after above two steps

20. Write Allocation  What should happen on a write miss? l The block we need to write does not exist in cache at this time  For write-through, two alternatives l Write Allocate(Allocate on miss): fetch the block, then overwrite the word in the block  continue write-through to lower level l No Write Allocate(Write around): update the word in memory but not bring into cache -Since programs often write a whole block before reading it (e.g., initialization—OS zeros entire page)—would perform better in this case  For write-back l Usually fetch the block and write the word and make the block dirty

21. Review: Why Pipeline? For Throughput! I n s t r. O r d e r Time (clock cycles) Inst 0 Inst 1 Inst 2 Inst 4 Inst 3 ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU I$ Reg D$Reg To keep the pipeline running at its maximum rate both I$ and D$ need to satisfy a request from the datapath every cycle. What happens when they can’t do that? Stall the pipeline  To avoid a structural hazard need two caches on-chip: one for instructions (I$) and one for data (D$)

22. Another Reference String Mapping 0404 0 404  Consider the main memory word reference string 0 4 0 4 0 4 0 4 Start with an empty cache - all blocks initially marked as not valid

23. Another Reference String Mapping 0404 0 404  Consider the main memory word reference string 0 4 0 4 0 4 0 4 miss 00 Mem(0) 01 4 01 Mem(4) 0 00 00 Mem(0) 01 4 00 Mem(0) 01 4 00 Mem(0) 01 4 01 Mem(4) 0 00 01 Mem(4) 0 00 Start with an empty cache - all blocks initially marked as not valid  Ping pong effect due to conflict misses - two memory locations that map into the same cache block l 8 requests, 8 misses

24. Sources of Cache Misses  Compulsory (cold start or process migration, first reference): l First access to a block, “cold” fact of life, not a whole lot you can do about it l If you are going to run “millions” of instruction, compulsory misses are insignificant  Conflict (collision): l Multiple memory locations mapped to the same cache location l Solution 1: increase cache size l Solution 2: increase associativity (later)  Capacity: l Cache cannot contain all blocks accessed by the program l Solution: increase cache size

25. Handling Cache Misses  Read misses (I$ and D$) l stall the entire pipeline, fetch the block from the next level in the memory hierarchy, install it in the cache and send the requested word to the processor, then let the pipeline resume  Write misses (D$ only) For write-through, two alternatives l Write Allocate(Allocate on miss): fetch the block, then overwrite the word in the block  continue write-through to lower level l No Write Allocate(Write around): update the word in memory but not bring into cache -Since programs often write a whole block before reading it (e.g., initialization—OS zeros entire page) For write-back l Usually fetch the block and write the word and make the block dirty

26. Multiword Block Direct Mapped Cache 8 Index Data IndexTagValid 0 1 2. 253 254 255 31 30... 13 12 11... 4 3 2 1 0 Byte offset 20 Tag HitData 32 Block offset  Four words/block, cache size = 1K words What is this?mux

27. Block Size Considerations  Larger blocks should reduce miss rate l Due to spatial locality  But in a fixed-sized cache l Larger blocks  fewer of them -More competition  increased miss rate -A needed block may be kicked out before spatial locality is exploited  Larger miss penalty l Can override benefit of reduced miss rate

28. Taking Advantage of Spatial Locality 0  Let cache block hold more than one word 0 1 2 3 4 3 4 15 1 2 343 415 Start with an empty cache - all blocks initially marked as not valid

29. Taking Advantage of Spatial Locality 0  Let cache block hold more than one word 0 1 2 3 4 3 4 15 1 2 343 415 00 Mem(1) Mem(0) miss 00 Mem(1) Mem(0) hit 00 Mem(3) Mem(2) 00 Mem(1) Mem(0) miss hit 00 Mem(3) Mem(2) 00 Mem(1) Mem(0) miss 00 Mem(3) Mem(2) 00 Mem(1) Mem(0) 01 54 hit 00 Mem(3) Mem(2) 01 Mem(5) Mem(4) hit 00 Mem(3) Mem(2) 01 Mem(5) Mem(4) 00 Mem(3) Mem(2) 01 Mem(5) Mem(4) miss 11 1514 Start with an empty cache - all blocks initially marked as not valid l 8 requests, 4 misses

30. Miss Rate vs Block Size vs Cache Size  Miss rate goes up if the block size becomes a significant fraction of the cache size because the number of blocks that can be held in the same size cache is smaller (increasing capacity misses)

31. Block Size Tradeoff l Larger block size means larger miss penalty -Latency to first word in block + transfer time for remaining words Miss Penalty Block Size Miss Rate Exploits Spatial Locality Fewer blocks compromises Temporal Locality Block Size Average Access Time Increased Miss Penalty & Miss Rate Block Size  In general, Average Memory Access Time = Hit Time + Miss Penalty x Miss Rate  Larger block sizes take advantage of spatial locality but l If the block size is too big relative to the cache size, the miss rate will go up

32. Multiword Block Considerations  Read misses (I$ and D$) l Processed the same as for single word blocks – a miss returns the entire block from memory l Miss penalty grows as block size grows—To reduce penalty  -Early restart – datapath resumes execution as soon as the requested word of the block is returned -Requested word first – requested word is transferred from the memory to the cache (and datapath) first l Nonblocking cache – allows the datapath to continue to access the cache while the cache is handling an earlier miss  Write misses (D$) l Since the block not in cache, we can’t use write the word or will end up with a “garbled” block in the cache (e.g., for 4 word blocks, a new tag, one word of data from the new block, and three words of data from the old block), so must fetch the block from memory first and pay the stall time

33. Cache Summary  The Principle of Locality: l Program likely to access a relatively small portion of the address space at any instant of time -Temporal Locality: Locality in Time -Spatial Locality: Locality in Space  Three major categories of cache misses: l Compulsory misses: sad facts of life. Example: cold start misses l Conflict misses: increase cache size and/or associativity Nightmare Scenario: ping pong effect! l Capacity misses: increase cache size  Cache design space l total size, block size, associativity (replacement policy) l write-hit policy (write-through, write-back) l write-miss policy (write allocate, write buffers)

34. Review: The Memory Hierarchy Increasing distance from the processor in access time L1$ L2$ Main Memory Secondary Memory Processor (Relative) size of the memory at each level Inclusive– what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM 4-8 bytes (word) 1 to 4 blocks 1,024+ bytes (disk sector = page) 8-32 bytes (block)  Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology

35. Review: Principle of Locality  Temporal Locality l Keep most recently accessed data items closer to the processor  Spatial Locality l Move blocks consisting of contiguous words to the upper levels  Hit Time << Miss Penalty l Hit: data appears in some block in the upper level (Blk X) -Hit Rate: the fraction of accesses found in the upper level -Hit Time: RAM access time + Time to determine hit/miss l Miss: data needs to be retrieve from a lower level block (Blk Y) -Miss Rate = 1 - (Hit Rate) -Miss Penalty: Time to replace a block in the upper level with a block from the lower level + Time to deliver this block’s word to the processor -Miss Types: Compulsory, Conflict, Capacity Lower Level Memory Upper Level Memory To Processor From Processor Blk X Blk Y

36. Measuring Cache Performance  Assuming cache hit costs are included as part of the normal CPU execution cycle, then CPU time = IC × CPI × CC = IC × (CPI ideal + Memory-stall cycles) × CC CPI stall  Memory-stall cycles come from cache misses (a sum of read-stalls and write-stalls) for writeback caches Read-stall cycles = reads/program × read miss rate × read miss penalty Write-stall cycles = (writes/program × write miss rate × write miss penalty) + write buffer stalls  For write-through caches, we can simplify this to Memory-stall cycles = miss rate × miss penalty IC: Inst Count CPI: Clock Cycles per Inst CC: Clock Cycle time

37. The “Memory Wall” bottleneck  Core logic(CPU) vs DRAM speed gap continues to grow  Performance of cache memory is becoming more important Clocks per instruction Clocks per DRAM access

38. Impacts of Cache Performance  Relative cache penalty increases as processor performance improves (faster clock rate and/or lower CPI) l The memory speed is unlikely to improve as fast as processor cycle time. When calculating CPI stall, the cache miss penalty is measured in processor clock cycles needed to handle a miss l The lower the CPI ideal, the more pronounced the impact of stalls  A processor with a CPI ideal of 2, a 100 cycle miss penalty, 36% load/store instr’s, and 2% I$ and 4% D$ miss rates Memory-stall cycles = 2% × 100 + 36% × 4% × 100 = 3.44 So CPI stalls = 2 + 3.44 = 5.44  What if the CPI ideal is reduced to 1? 0.5? 0.25?  What if the processor clock rate is doubled?  doubling the miss penalty

39. Reducing Cache Miss Rates #1 1. Allow more flexible block placement  In a direct mapped cache a memory block maps to exactly one cache block  At the other extreme, could allow a memory block to be mapped to any cache block – fully associative cache  A compromise is to divide the cache into sets each of which consists of n “ways” (n-way set associative). A memory block maps to a unique set (specified by the index field) and can be placed in any way of that set (so there are n choices) (block address) modulo (# sets in the cache)

40. Set Associative Cache Example 0 Cache Main Memory Q2: How do we find it? Use next 1 low order memory address bit to determine which cache set (i.e., modulo the number of sets in the cache) TagData Q1: Is it there? Compare all the cache tags in the set to the high order 3 memory address bits to tell if the memory block is in the cache V 0000xx 0001xx 0010xx 0011xx 0100xx 0101xx 0110xx 0111xx 1000xx 1001xx 1010xx 1011xx 1100xx 1101xx 1110xx 1111xx Two low order bits(xx) define the byte in the word (32-b words) One word blocks Set 1 0 1 2-Way 0 1

41. Another Reference String Mapping 0404  Consider the main memory word reference string 0 4 0 4 0 4 0 4 Start with an empty cache - all blocks initially marked as not valid Set 0 Set 1 Set 0 Set 1 Set 0 Set 1 Set 0 Set 1

42. Another Reference String Mapping 0404  Consider the main memory word reference string 0 4 0 4 0 4 0 4 miss hit 000 Mem(0) Start with an empty cache - all blocks initially marked as not valid 010 Mem(4) 000 Mem(0) 010 Mem(4)  Solves the ping pong effect(slide 15) in a direct mapped cache due to conflict misses since now two memory locations that map into the same cache set can co-exist! l 8 requests, 2 misses …….

43. Four-Way Set Associative Cache  2 8 = 256 sets each with four ways (each with one block) 31 30... 13 12 11... 2 1 0 Byte offset Data TagV 0 1 2. 253 254 255 Data TagV 0 1 2. 253 254 255 Data TagV 0 1 2. 253 254 255 Index Data TagV 0 1 2. 253 254 255 8 Index 22 Tag HitData 32 4x1 select Block size= ?1 word

44. Spectrum of Associativity Block offsetByte offsetIndexTag When a block contains more than one word One important point is that the total size of cache is fixed Given size of cache= 8 entries

45. Range of Set Associative Caches  For a fixed size cache, each increase by a factor of two in associativity doubles the number of blocks per set (i.e., the number or ways) and halves the number of sets – decreases the size of the index by 1 bit and increases the size of the tag by 1 bit Block offsetByte offsetIndexTag Decreasing associativity Fully associative (only one set) Tag is all the bits except block and byte offset Direct mapped (only one way) Smaller tags Increasing associativity Selects the setUsed for tag compareSelects the word in the block

46. Costs of Set Associative Caches  When a miss occurs, which way’s block do we pick for replacement? l Least Recently Used (LRU): the block replaced is the one that has been unused for the longest time -Must have hardware to keep track of when each way’s block was used relative to the other blocks in the set -For 2-way set associative, takes one bit per set → set the bit when a block is referenced (and reset the other way’s bit)  N-way set associative cache costs l N comparators (delay and area) l MUX delay (set selection) before data is available l Data available after set selection (and Hit/Miss decision). In a direct mapped cache, the cache block is available before the Hit/Miss decision -So its not possible to just assume a hit and continue and recover later if it was a miss

47. Benefits of Set Associative Caches  The choice of direct mapped or set associative depends on the cost of a miss versus the cost of implementation Data from Hennessy & Patterson, Computer Architecture, 2003  Largest gains are in going from direct mapped to 2-way (20%+ reduction in miss rate)

48. Reducing Cache Miss Rates #2 (#1=associativity) 2. Use multiple levels of caches  With advancing technology have more than enough room on the die for bigger L1 caches or for a second level of caches – normally a unified L2 cache (i.e., it holds both instructions and data) and in some cases even a unified L3 cache on chip  For our example, CPI ideal of 2, 100 cycle miss penalty (to main memory), 36% load/stores, a 2% (4%) L1I$ (D$) miss rate, add a L2$ that has a 25 cycle miss penalty and a 0.5% miss rate CPI stalls = 2 +.02×25 +.36×.04×25 +.005×100 +.36×.005×100 = 3.54 (as compared to 5.44(slide 38) with no L2$) L2 miss for inst L2 miss for data

49. Multilevel Cache Design Considerations  Design considerations for L1 and L2 caches are very different l Primary cache(L1$) should focus on minimizing hit time in support of a shorter clock cycle -Smaller with smaller block sizes l Secondary cache(s)(L2$ & L3$) should focus on reducing miss rate to reduce the penalty of long main memory access times -Larger with larger block sizes  The miss penalty of the L1 cache is significantly reduced by the presence of an L2 cache – so it can be smaller (i.e., faster) but have a higher miss rate  For the L2 cache, hit time is less important than miss rate

50. Key Cache Design Parameters L1 typicalL2 typical Total size (blocks)250 to 20004000 to 250,000 Total size (KB)16 to 64500 to 8000 Block size (B)32 to 6432 to 128 Miss penalty (clocks)10 to 25100 to 1000 Miss rates2% to 5%0.1% to 2%

51. Two Machines’ Cache Parameters Intel P4AMD Opteron L1 organizationSplit I$ and D$ L1 cache size8KB for D$, 96KB for trace cache (~I$) 64KB for each of I$ and D$ L1 block size64 bytes L1 associativity4-way set assoc.2-way set assoc. L1 replacement~ LRULRU L1 write policywrite-throughwrite-back L2 organizationUnified L2 cache size512KB1024KB (1MB) L2 block size128 bytes64 bytes L2 associativity8-way set assoc.16-way set assoc. L2 replacement~LRU L2 write policywrite-back

52. Why Multilevel caches?  Rather than having L1 & L2 caches on chip, how about increasing the size of L1 cache? L1L2 L1 Smaller is Faster CPU

53. IBM Power 5 cache Not on chip— but L3 control logic is on chip L1

54. IBM Power 5 die

55.  IBM POWER5 MCM(Multi-Chip Module) with four processors and four 36 MB external L3 cache modules.POWER5 Processor Cache Next will be Power7 --2 chips per module--8 cores per chip --4 threads per core (32 threads per chip)Power7

56. 4 Questions for the Memory Hierarchy  Q1: Where can a block be placed in the upper level? (Block placement)  Q2: How is a block found if it is in the upper level? (Block identification)  Q3: Which block should be replaced on a miss? (Block replacement)  Q4: What happens on a write? (Write strategy)

57. Q1&Q2: Where can a block be placed/found? # of setsBlocks per set Direct mapped# of blocks in cache1 Set associative(# of blocks in cache)/ associativity Associativity (typically 2 to 16) Fully associative1# of blocks in cache Location method# of comparisons Direct mappedIndex1 Set associativeIndex the set; compare set’s tags Degree of associativity Fully associativeCompare all blocks tags# of blocks

58. Q3: Which block should be replaced on a miss?  Easy for direct mapped – only one choice  Set associative or fully associative l Random l LRU (Least Recently Used)  For a 2-way set associative cache, random replacement has a miss rate about 1.1 times higher than LRU.  LRU is too costly to implement for high levels of associativity (> 4-way) since tracking the usage information is costly

59. Q4: What happens on a write?  Write-through – The information is written to both the block in the cache and to the block in the next lower level of the memory hierarchy l Write-through is always combined with a write buffer so write waits to lower level memory can be eliminated (as long as the write buffer doesn’t fill)  Write-back – The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. l Need a dirty bit to keep track of whether the block is clean or dirty  Pros and cons of each? l Write-through: read misses don’t result in writes (so are simpler and cheaper) l Write-back: repeated writes require only one write to lower level

60. Improving Cache Performance 0. Reduce the time to hit in the cache l smaller cache l direct mapped cache l smaller blocks l for writes -no write allocate – no “hit” on cache, just write to write buffer -write allocate – to avoid two cycles (first check for hit, then write) pipeline writes via a delayed write buffer to cache 1. Reduce the miss rate l bigger cache l more flexible placement (increase associativity) l larger blocks (16 to 64 bytes typical) l victim cache – small buffer holding most recently discarded blocks

61. Improving Cache Performance 2. Reduce the miss penalty l smaller blocks l use a write buffer to hold dirty blocks being replaced so don’t have to wait for the write to complete before reading l check write buffer (and/or victim cache) on read miss – may get lucky to find it l for large blocks fetch critical word first l use multiple cache levels – L2 cache not tied to CPU clock rate l faster backing store/improved memory bandwidth -wider buses -memory interleaving, page mode DRAMs

62. Review: The Memory Hierarchy Increasing distance from the processor in access time L1$ L2$ Main Memory Secondary Memory Processor (Relative) size of the memory at each level Inclusive– what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM 4-8 bytes (word) 1 to 4 blocks 1,024+ bytes (disk sector = page) 8-32 bytes (block)  Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology Cache memory Virtual memory

63. Virtual Memory  Use main memory as a “cache” for secondary memory(disk) l Allows efficient and safe sharing of memory among multiple programs l Provides the ability to easily run programs larger than the size of physical memory l Simplifies loading a program for execution by providing for code relocation (i.e., the code can be loaded anywhere in main memory)  What makes it work? – again the Principle of Locality l A program is likely to access a relatively small portion of its address space during any period of time  Each program is compiled into its own address space – a “virtual” address space l During run-time each virtual address must be translated to a physical address (an address in main memory)—by CPU & OS l VM “block” = page, VM “miss” = page fault

64. Two Programs Sharing Physical Memory Program 1 virtual address space main memory  A program’s address space is divided into pages (all one fixed size) or segments (variable sizes) l The starting location of each page (either in main memory or in secondary memory) is contained in the program’s page table Program 2 virtual address space Open Windows Task Manager to see processes Also, Administrative Tools  Performance

65. Another view from wiki A program’s address space

66. Address Translation Virtual Address (VA) seen by CPU Page offsetVirtual page number 31 30... 12 11... 0 Page offsetPhysical page number Physical Address (PA) 29... 12 11 0 Translation  So each memory request first requires an address translation from the virtual space to the physical space l A virtual memory miss (i.e., when the page is not in physical memory) is called a page fault  A virtual address is translated to a physical address(in memory) by a combination of hardware and software Assuming 4K bytes per page Assuming 1G bytes memory

67. Another view(Figure 5.21)

68. Address Translation Mechanisms Physical page base addr Main memory Disk storage Virtual page # V 1111110101011111101010 Page Table (in main memory) Offset Physical page # Offset

69. Page Fault Penalty  On page fault, the page must be fetched from disk l Takes millions of clock cycles l Handled by OS code  Try to minimize page fault rate l Fully associative placement l Smart replacement algorithms

70. Virtual Addressing with a Cache  Thus it takes an extra memory access to translate a VA to a PA CPU Trans- lation Cache Main Memory VAPA miss hit data  This makes memory (cache) accesses very expensive (if every access was really two accesses)  The hardware fix is to use a Translation Lookaside Buffer (TLB) – a small cache that keeps track of recently used address mappings to avoid having to do a page table lookup When we discussed cache, we did not include this step for simplicity

71. Fast Translation Using a TLB

72. Translation Lookaside Buffers (TLBs)  Just like any other cache, the TLB can be organized as direct mapped, set associative, fully associative V Virtual Page # Physical Page # Dirty Ref (Access)  TLB access time is typically smaller than cache access time (because TLBs are much smaller than caches) l TLBs are typically not more than 128 to 1024 entries even on high end machines l In the IBM POWER5 processor, the page table is cached in a 1,024-entry, four-way set-associative translation lookaside buffer (TLB).IBM POWER5 Used for LRU

73. A TLB in the Memory Hierarchy  A TLB miss – is it a page fault or merely a TLB miss? l If the page is loaded into main memory, then the TLB miss can be handled (in hardware or software) by loading the translation information from the page table(in memory) into the TLB -Takes 10’s of cycles to find and load the translation info into the TLB l If the page is not in main memory, then it’s a true page fault -Takes 1,000,000’s of cycles to service a page fault  TLB misses are much more frequent than true page faults CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss ¾ t ¼ t Assuming TLB is 3 times faster than cache

74. TLBs and caches

75. Modern Systems Physical Address Extension (PAE) PAE does not change the size of the virtual address space, which remains at 4 GB, just the amount of actual RAM that can be addressed by the processor.

76. Modern Systems

77. TLB Event Combinations TLBPage Table CachePossible? Under what circumstances? Hit Miss Hit MissHitMiss HitMissMiss/ Hit Miss Hit

78. TLB Event Combinations TLBPage Table CachePossible? Under what circumstances? Hit Miss Hit MissHitMiss HitMissMiss/ Hit Miss Hit Yes – what we want! Yes – although the page table is not checked if the TLB hit occurs Yes – TLB miss, PA in page table Yes – TLB miss, PA in page table, but data not in cache but in memory Yes – page fault Impossible – TLB translation not possible if page is not present in memory Impossible – data not allowed in cache if page is not in memory

79. Reducing Translation Time  Can overlap the cache access with the TLB access l Works when the high order bits of the VA are used to access the TLB while the low order bits are used as index into cache TagData = TagData = Cache HitDesired word VA Tag PA Tag TLB Hit 2-way Associative Cache Index PA Tag Block offset

80. The Hardware/Software Boundary  What parts of the virtual to physical address translation is done by or assisted by hardware? l Translation Lookaside Buffer (TLB) that caches the recent translations -TLB access time is part of the cache hit time -May allocate an extra stage in the pipeline for TLB access l Page table storage, fault detection and updating -Page faults result in interrupts (precise) that are then handled by the OS -Hardware must support (i.e., update appropriately) Dirty and Reference bits (e.g., ~LRU) in the Page Tables l Disk placement -Bootstrap (e.g., out of disk sector 0) so the system can service a limited number of page faults before the OS is even loaded

81. From http://support.microsoft.com/kb/555223 about Windows pagefile.syshttp://support.microsoft.com/kb/555223  RAM is a limited resource, whereas virtual memory is, for most practical purposes, unlimited. There can be a large number of processes each with its own 2 GB of private virtual address space. When the memory in use by all the existing processes exceeds the amount of RAM available, the operating system will move pages (4 KB pieces) of one or more virtual address spaces to the computer’s hard disk, thus freeing that RAM frame for other uses. In Windows systems, these “paged out” pages are stored in one or more files called pagefile.sys in the root of a partition. There can be one such file in each disk partition.

82. Summary  The Principle of Locality: l Program likely to access a relatively small portion of the address space at any instant of time. -Temporal Locality: Locality in Time -Spatial Locality: Locality in Space  Caches, TLBs, Virtual Memory all understood by examining how they deal with the four questions 1. Where can block be placed? 2. How is block found? 3. What block is replaced on miss? 4. How are writes handled?  Page tables map virtual address to physical address l TLBs are important for fast translation

83. Virtual Machines  Host computer emulates guest operating system and machine resources l Improved isolation of multiple guests l Avoids security and reliability problems l Aids sharing of resources  Virtualization has some performance impact l Feasible with modern high-performance comptuers  Examples l IBM VM/370 (1970s technology!) l VMWare l Microsoft Virtual PC §5.6 Virtual Machines

84. Virtual Machine Monitor  Maps virtual resources to physical resources l Memory, I/O devices, CPUs  Guest code runs on native machine in user mode l Traps to VMM on privileged instructions and access to protected resources  Guest OS may be different from host OS  VMM handles real I/O devices l Emulates generic virtual I/O devices for guest