1. Performed by: Tziki Oz-Sinay, Ori Lempel Instructor: Rony Mitleman המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering סמסטרים חורף וקיץ תשס " ד 1 ARMOR Asynchronous RISC Microprocessor

2. Abstract המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory 2 The benefits of asynchronous VLSI circuit design include: elimination of clock skew problems, average-case performance, adaptivity to processing and environmental variations, lower system power requirements and reduced noise. The ARMOR is an asynchronous RISC microprocessor with an out-of-order execution engine. It is designed using the Balsa asynchronous hardware description language and environment tools. The synthesized ARMOR core may then be implemented on the Xilinx VertexPro FPGA and interface with synchronous memory modules.

3. System Description המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory 3 ARMOR core SDRAM 64KB SDRAM 64KB PCI Interface Data Cache Inst Cache Watch Window (debug) Program Code (assembler) Xilinx VertexPro

4. ARMOR Pipeline המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory 5 Instruction Fetch Decode Rename Mem Access Write Back Execute Retire PC[15:0] Inst[15:0] Op[3:0] LDst[3:0] LSrc[3:0] Imm[15:0] Op[3:0] PDst[4:0] SrcVal1[15:0 ] SrcVal2[15:0] Imm[15:0] DataIn[15:0] PDst[4:0] Addr[15:0] ReadWrite# ALU0PDst[4:0] ALU0Res[15:0] ALU1PDst[4:0] ALU1Res[15:0] MemPDst[4:0] DataOut[15:0] LDst[2:0] Val15:0] Op[3:0] PDst[4:0] SrcVal1[15:0 ] SrcVal2[15:0] Imm[15:0] BranchDecision Out Of Order Engine SYNCHRONIZATION SDRAM Addr[15:0] DataIn[15:0] DataOut[15:0] SDRAM

5. ARMOR Out-Of-Order Engine המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory 5 ROB RRF RAT RS0RS1 ALU0ALU1 DATA CACHE BranchDecision to IFU Inst from ID In Order Out of Order branches non-mem inst mem inst non-branch inst