1. A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits Hao Yu, Yiyu Shi, Lei He Electrical Engineering Dept. UCLA David Smart Analog Devices Inc. Partially supported by NSF, SRC and UC-MICRO fund

2. 2 Challenge to Model Inductance n Loop inductance? l Where is the return path? Current return paths are not known as a priori l How to stamp a loop inductance together with other devices in the same loop to the circuit matrix? n Partial inductance by PEEC [Rueli:TMTT’74] is one choice for inductive interconnect c4 bump on die Power grid signal lines C4 package Power Plane skin depth current return current

3. 3 PEEC Model for Interconnect n No need to determine return path l But did we really solve the problem? n Partial inductance is associated with every piece of branch current l Mutual couplings are everywhere l L matrix is dense and not diagonal dominant n A fast simulator needs a sparse stamping of devices l Sparsifying L by truncation leads to the loss of stability n Stamping inverse inductance (L -1 ) element is an alternative solution l L -1 is similar to the diagonal dominant capacitance (C) [Devgan:ICCAD’02], and hence it is easy to sparsify l How to stamp it correctly in circuit matrix? How to further reduce it by model order reduction?

4. 4 Inverse Inductance Element Simulation n First-order stamping and reduction by modified nodal analysis (MNA) l Directly stamping leads to a non-passive model [Zheng et.al.:ICCAD’02] l Double inversion based stamping [Chen,et.al.: ICCAD’03] needs an extra cost to invert L matrix n Second-order stamping and reduction by nodal analysis (NA) l NA-stamping [Sheehan:DAC99, Zheng et.al :ICCAD’02, Su et. al:ICCAD’04] has singularity at dc, and is not robust to be stamped back for time domain simulation l All above methods did not consider the structure (sparsity and hierarchy), and hence are not efficient for large-scale problem n Primary contributions of our work: 1. Vector potential nodal analysis (VNA) represents L -1 in a non- singular and passive stamping 2. Bordered-block-diagonal structured reduction (BVOR) preserves not only passivity but also sparsity and hierarchy

5. 5 Outline n Background of Circuit Stamping n VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model n BVOR Method using BBD (Bordered-block- diagonal) Representation n Experimental Results n Conclusions

6. 6 Modified Nodal Analysis n A network is described by two state variables: nodal voltage and branch current vn+vn+ Vn - IbIb R n The stamping is not symmetric but passive l Check (and full rank) n The stamping is non-singular l State equation is still definite at dc  L is shorted and C is open at dc l State matrix is not rank-deficient u especially for because it needs to be factorized many times

7. 7 Stamping of L-Inverse in Circuit Matrix n MNA is not passive l Check n NA stamping is symmetric, seems to be passive, but is singular Only uses nodal voltages, and it results in a susceptance S for L -1 l State equation is indefinite at dc Both G and S become rank-deficient in NA stamping

8. 8 NA How to Easily Have a Singular Stamping n Why do we need branch current variable for inductance? l The inductor is shorted at dc v2 and v3 are not independent anymore  Need a new constraint by adding a new row for i1 RgRg RL v1 v2 v3 i1 ( 1/Rg+1/R) (-1/R) (0) (0) (-1/R) (1/R) (0) 1 (0) (0) (0) -1 (0) (-1) (1) sL v1 v2 v3 i1

9. 9 Outline n Background of Circuit Stamping n VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model n BVOR Method using BBD (Bordered-block- diagonal) Representation n Experimental Results n Conclusions

10. 10 Vector Potential Equivalent Circuit n Differential Maxell equation n Define branch vector potential (flux) from a volume- integral of above differential equation [Pacelli:ICCAD’02] VPEC circuit equation describes L -1 elements using branch variables ( i i, v i ) n This leads to the proof that L -1 matrix is diagonal dominant [Yu-He:TCAD’05]

11. 11 VNA Stamping n Using both branch and nodal variables, VPEC circuit equation leads to a new circuit stamping for L -1 n The resulting VNA state matrix is non-singular and passive

12. 12 A Circuit Example VNA a2 a1 v6 v5 v4 v3 v2 1v1 p2p1 v6 v5 v4 v3 1 v2 1v1 p2p1 i2 i1 v6 -g v5 -gv4 -1v3 1 -g v2 -gv1 i2i1v6v5v4v3v2v1 v6 v5 -g g v4 v3 v2 g +gd v1 v6v54 1 -1 -11 -11lmi2 mli1 cv6 v5 cx-cxv4 cv3 v2 -cxcxv1 i2i1v6v5v4v3v2v1 cv6 v5 cx-cxv4 cv3 v2 -cxcxv1 v6v5v4v3v2v1 g ( a ) (b ) (c) g + MNA NA cv6 v5 cx- v4 cv3 v2 -cx v1 v6v5v4v3v2v1 cv6 v5 cx- v4 cv3 v2 -cx v1 v6v5v4v3v2v1 s-ssx- v6 -ss-sx v5 v4 sx- s-sv3 -sx -ssv2 v1 v6v5v4v3v2v1 s-ssx- v6 -ss-sx v5 v4 sx- s-sv3 -sx -ssv2 v1 v6v5v4v3v2v1 v6 v5 v4 v3 1 v2 1v1 p2p1 v6 v5 v4 v3 v2 1v1 v6 -g v5 -gv4 v3 -gv2 -gv1 v6v5v4v3v2v1 v6 v5 v4 v3 -gv2 -gv1 v6v5v4v3v2v1 g g (a) (b) (c) (d) g+gd g+gd

13. 13 VNA Reduction (VOR) n The simple first-order model order reduction such as PRIMA [Odabasioglu,et.al:TCAD’98] can be applied Find a small dimensioned and orthnormalized matrix V to reduce the original system size by projection n If V contains the subspace of moments, the reduced system can match the original system NxN qxq qxN

14. 14 Advantages of VNA Reduction n The reduced model is passive l Sufficient conditions for passivity: n The VNA reduction can be performed at dc (s0=0), and hence the path tracing algorithm [Odabasioglu,et.al:TCAD’98] can be used for efficient reduction n The reduced model by VNA can be robustly stamped together with active device for time-domain simulation l SAPOR is not robust to be stamped back with active devices

15. 15 Outline n Background of Circuit Stamping n VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model n BVOR Method using BBD (Bordered-block- diagonal) Representation n Experimental Results n Conclusions

16. 16 Two Level Decomposition by Branch Tearing n A flat presentation of VNA does not show hierarchy and hence leads to a globalized reduction and simulation l It is not efficient for large-scale circuit with inductance l Path-tracing [Odabasioglu,et.al:TCAD’98] is only effective for tree-links but not for general network n Two-level decomposition of VNA circuit by branch- tearing It results in decomposed blocks Y i and a global block Z 0, and they are interconnected by incident matrix X i0 l The torn branch can be a resistor, a capacitor, or an inductor l A hmetis partition is applied with specified ports for each block

17. 17 BBD Representation n The resulting system is in fact a bordered-block-diagonal (BBD) state matrices Each block Yi is described by a set of VNA variables ( v n, A l ) The global block Z0 is described by a set of torn branch variables ( i b ) n The BBD stamping is passive

18. 18 BVOR: Localized Reduction n BBD representation enables a localized model order reduction Each block Yi ( Gi, Ci, Bi ) can be reduced locally l The last block is purely composed by coupling branches, which is projected by an identity matrix n Reduced model is not only passive but also sparse, and it can be analyzed hierarchically n Block-diagonal structured projection [Yu-He-Tan:BMAS’05] preserves BBD structure during reduction

19. 19 Outline n Background of Circuit Stamping n VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model n BVOR Method using BBD (Bordered-block- diagonal) Representation n Experimental Results n Conclusions

20. 20 Waveform Comparison (1) n Frequency/time domain waveform comparison of full- MNA, SAPOR [Su et.al:ICCAD’04] and VNA reduction (VOR) l The reduced models are expanded close to dc (s0 = 10Hz) with order 80 l VOR and original are visually identical in both time/frequency domain l SAPOR has larger frequency-domain error and can not converge in time- domain simulation

21. 21 Waveform Comparison (2) n Frequency domain waveform in both low and high frequency range l The reduced models are expanded at s0 = 1GHz with order 80 l VOR is identical to the original in both ranges, l But SAPOR has large error in low-frequency range.

22. 22 BBD Structure Preserving n BBD (two-level decomposition) representation and reduction of G and C matrices l The reduced model has preserved sparsity and BBD structure

23. 23 Runtime Scalability Study of BVOR n Compared to SAPOR, BVOR (BBD reduction) is 23X faster to build, 30X faster to simulate, and has 51X smaller error n Compared to VOR, BVOR is 12X faster to build, 30X faster to simulate

24. 24 Conclusions and Future Work n Propose a new circuit stamping (VNA) for L-inverse element, which is passive and non-singular n Apply a bordered-block-diagonal (BBD) structured reduction, which enables a localized model order reduction for large scale RCL -1 circuits We are planning to extend the structured reduction to handle nonlinear system