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Vector Potential Equivalent Circuit Based on PEEC Inversion Hao Yu and Lei He Electrical Engineering Department, UCLA http://eda.ee.ucla.edu Partially Sponsored by NSF Career Award (0093273), and UC-Micro fund from Analog Devices, Intel and LSI Logic

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Outline Introduction Vector Potential Equivalent Circuit Model VPEC Property and Sparsification Conclusions and Future Work

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Interconnect Model de facto PEEC model is expensive Total 3,278,080 elements for 128b bus with 20 segments per line 162M storage of SPICE netlist small surface panels with constant charge thin volume filaments with constant current Accurate model needs detailed discretization of conductors Distributed RLC circuit has coupling inductance between any two segments

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Challenge of Inductance Sparisification Existing passivity-guaranteed sparsification methods lack accuracy or theoretical justification Returned-loop [Shepard:TCAD’00] Shift-truncation (shell) [Krauter:ICCAD’95] K-element [Devgan:ICCAD’00] Localized VPEC [Pacelli:ICCAD’02] Partial inductance matrix L is not diagonal dominant Direct truncation results loss of passivity

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K-Element Method K-method Observe that the inversion of L is M-matrix [Devgan:ICCAD’00] Need to extend SPICE to simulate K-element [ Ji: DAC’01] Windowing Extract the K-elements of sub-matrices to avoid full inversion [Beattie: DATE’01] Wire-duplication Improve the accuracy of windowing method [Zhong: ICCAD’02, DAC’03] Inductwise Heuristic bi-section the longest wire to guarantee K as M-matrix [Chen:ICCAD’02]

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Contribution of Our Paper Prove that circuit matrix in VPEC model is strictly diagonal dominant and hence passive Enable various passivity preserved sparsifications Derive inversion based VPEC model from first principles Replace inductances with effective magnetic resistances Develop closed-form formula for effective resistances Enable direct and faster simulation in SPICE

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Outline Introduction Vector Potential Equivalent Circuit Model VPEC Property and Sparsification Conclusions and Future Work VPEC circuit model Inversion based VPEC Accuracy comparison

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Vector Potential Equations for Inductive Effect Vector potential for filament i ith Filament Integral equation for inductive effect Volume Integration Line Integration

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VPEC model for any two filaments VPEC Circuit Model Effective Resistances

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VPEC model for two filaments VPEC Circuit Model Vector Potential Current Source

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VPEC Circuit Model VPEC model for two filaments Vector Potential Voltage Source

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Recap of VPEC Circuit Model Inherit resistances and capacitances from PEEC Inductances are modeled by: Effective resistances Controlled current/voltage sources Unit self-inductance Much fewer reactive elements leads to faster SPICE simulation

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Comparison with Localized VPEC Our solution (1) It is not accurate to consider only adjacent filaments Solution in localized VPEC [Pacelli:ICCAD’02] (2) There is no efficient and closed-form formula solution to calculate effective resistances

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Introduction of G-Element

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Closed-form Formula for Effective Resistance Major computing effort is inversion of inductance matrix LU/Cholesky factorization GMRES/GCR iteration (with volume decomposition) System equation based on G-element System equation based on K-element i.e. Inversion Based VPEC

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Interconnect Analysis Based on VPEC 1.Calculate PEEC elements via either formula or FastHenry/FastCap 2.Invert L matrix 3. Generate full VPEC including effective resistances, current and voltage sources. 4. Sparsify full VPEC using numerical or geometrical truncations 5. Directly simulate in SPICE PEEC (R,L,C) L^(-1) Full VPEC Sparsified VPEC SPICE Simulation

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Spice Waveform Comparison Full PEEC vs. full VPEC vs. localized VPEC Full VPEC is as accurate as Full PEEC Localized VPEC model is not accurate

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Spiral Inductor Non-bus Structure: Three-turn single layer on-chip spiral inductor Full VPEC model is accurate and can be applied for general layout

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Outline Introduction Vector Potential Equivalent Circuit Model VPEC Property and Sparsification Conclusions and Future Work

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Property of VPEC Circuit Matrix Main Theorem The circuit matrix is strictly diagonal-dominant and positive-definite Corollary The VPEC model is still passive after truncation Sketch proof:

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Numerical Sparsification Example: truncation of 5-bit bus with threshold 0.09 Drop off-diagonal elements with ratio below the threshold Larger effective resistors are less sensitive to current change Calculate the ratio between off-diagonal elements and the diagonal element of every row Given the full matrix

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Truncation Threshold Supply voltage is 1V VPEC runtime includes the LU inversion Full VPEC model is as accurate as full PEEC model but yet faster Increased truncation ratio leads to reduced runtime and accuracy Models and Settings (threshold) No. of Elements Run-time (s)Average Volt. Diff. (V) Standard Dev. (V) Full PEEC 8256281.020V Full VPEC 825636.40-1.64e-6V3.41e-4V Truncated VPEC (5e-5) 748230.894.64e-6V4.97e-4V Truncated VPEC (1e-4) 539219.551.29e-5V1.37e-3V Truncated VPEC (5e-4) 25178.353.77e-4V5.20e-3V 128-bit bus with one segment per line

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Waveforms Comparison Full VPEC is as accurate as full PEEC Sparsified VPEC has high accuracy for up to 35.7% sparsification

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Geometry Based Sparsification - Windowed Windowed VPEC neighbor-window (nix, niy ) for aligned coupling and forwarded coupling consider only forward coupling of same wire For the geometry of aligned bus line

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Geometry Based Sparsification - Normalized Normalized VPEC normalized aligned coupling n: segments number

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Geometrical Sparsification Results 32-bit bus with 8 segment per line Decreased window size leads to reduced runtime and accuracy Windowed VPEC has high accuracy for window size as small as (16,2) Normalized model is still efficient with bounded error Models and Settings No. of Elements Run Time (s)Avg. Volt. Diff. (V) Standard Dev. (V) Full PEEC328962535.4800 Full VPEC (32, 8) 32896772.891.00e-56.26e-4 Windowed (32, 2) 11392311.225.97e-51.84e-3 Windowed (16, 2) 3488152.57-1.23e-44.56e-3 Windowed (8, 2)224085.14-2.17e-48.91e-3 Normalized4224255.36-6.05e-42.96e-3

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Runtime Scaling Circuit: one segment per line for buses The runtime grows much faster for full PEEC than for full VPEC full PEEC is 47x faster for 256-bit bus due to reduced number of reactive elements Sparsified VPEC reduces runtime by 1000x with bounded error for large scale interconnects

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Conclusions and Future Work Derived inversion based VPEC from first principle Shown that Full VPEC has the same accuracy as full PEEC but faster Proved that VPEC model remains passive after truncation To work on Fast iteration algorithms for inversion of L Model-order-reduction for VPEC (see ICCAD’2006)

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