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Published byGuillermo Smartt Modified over 3 years ago

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**Vector Potential Equivalent Circuit Based on PEEC Inversion**

Hao Yu and Lei He Electrical Engineering Department, UCLA Partially Sponsored by NSF Career Award ( ) , and UC-Micro fund from Analog Devices, Intel and LSI Logic

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**Outline Introduction Vector Potential Equivalent Circuit Model**

VPEC Property and Sparsification Conclusions and Future Work

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**Interconnect Model de facto PEEC model is expensive**

Accurate model needs detailed discretization of conductors Distributed RLC circuit has coupling inductance between any two segments Total 3,278,080 elements for 128b bus with 20 segments per line 162M storage of SPICE netlist small surface panels with constant charge thin volume filaments with constant current As we all know, the de dacto interconnet model is based on peec. As whon in the figure, the accurate peec model needs deialed … We needs the volume decopostion for non-uniform current distribution; and also surface decompstion for non-unifrom chage distruibusion; and finall we also needs segemnt the conductor along it s length due to quisa-staic approximation. Anotherhorribale fact is that there are lots of coupling inductances between any pairs of dicretized conductors. Therefore the complxicity of reslued peec circuits is very hgih. For exampe

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**Challenge of Inductance Sparisification**

Partial inductance matrix L is not diagonal dominant Direct truncation results loss of passivity Existing passivity-guaranteed sparsification methods lack accuracy or theoretical justification Returned-loop [Shepard:TCAD’00] Shift-truncation (shell) [Krauter:ICCAD’95] K-element [Devgan:ICCAD’00] Localized VPEC [Pacelli:ICCAD’02] Given the dense Lp it can’t be directly truncated since the Lp is not digonal dominant matrix. Therefore it becomes the bottlemneck for accurate pee simulation in spice. Therere lots of passivity-guranteed inductance sparsication mehtods such as … However most of them lack accuracy or theorectical justifications. Here I’ll breifly reviwew the k-elemnt mehthod.

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**K-Element Method K-method Windowing Wire-duplication Inductwise**

Observe that the inversion of L is M-matrix [Devgan:ICCAD’00] Need to extend SPICE to simulate K-element [Ji: DAC’01] Windowing Extract the K-elements of sub-matrices to avoid full inversion [Beattie: DATE’01] Wire-duplication Improve the accuracy of windowing method [Zhong: ICCAD’02, DAC’03] Inductwise Heuristic bi-section the longest wire to guarantee K as M-matrix [Chen:ICCAD’02] The k-ememnt mehtod isproposed by devagn two years agao. Bascilly they observe that the invesion of L matrix is a M-matrix, say all the off-dignal elemmnts are negtive,and all the digonal eleemnts are dominant. Acutally the matrix in this form will be strictly pdgonal domiant matrix. Futherempre, sinc ethe cirtcuit element has changed from L to K, we need extend the spice to handle the Kelement based simulation. The windfowing base dmehtd is prosed to extract the k-eleemnt (or suscpetance) of the sub-matrix to avoid the full inversion of L. howver It is obvious that the resluted elements are not accurate compared to results from full inversion. The wire-duplication mehtod is then poposed to impove the accuracy of such kind of windowing mehod. In some very special geometry settings, the obtained K matrix will not be strictly M-matrix. The inducwise has propose the Hruris bi-section of the longese wire to gurantted the k matrix as the M-matricx. Fiunally lots of interesting work has been propsoed for k-eement based model order reducction.

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**Contribution of Our Paper**

Derive inversion based VPEC model from first principles Replace inductances with effective magnetic resistances Develop closed-form formula for effective resistances Enable direct and faster simulation in SPICE Prove that circuit matrix in VPEC model is strictly diagonal dominant and hence passive Enable various passivity preserved sparsifications Plus additionall controlled sourses

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**Outline Introduction Vector Potential Equivalent Circuit Model**

VPEC Property and Sparsification Conclusions and Future Work VPEC circuit model Inversion based VPEC Accuracy comparison

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**Vector Potential Equations for Inductive Effect**

Vector potential for filament i ith Filament Integral equation for inductive effect Volume Integration Line Integration We use the filament assupmtion, say all the objects here are filaments with uniform current distribution along z-direction, and legnth l. Let’s then begin tow diffe maxwell equs. Where the first one is the possion-like spacially differnicl,and second is the time-dereivative equation. We then define the node vecto poteial as the average of total vector potential inside the controlled volume omen accociated with Ith filament. Based on these basicis, we can derive the following VPEC circuit equation.

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**VPEC Circuit Model VPEC model for any two filaments**

Effective Resistances VPEC model for any two filaments Here is the two staring equation, by aobve basiss we obatin the folwlong vpec circuit eqations. Let’s give an example of vpec circuit model Of two filaments to illustrate the inside circuit element. First note that the wire rsitances and cpacirtance are still the same in peec model. we use effective resitances to account for the effect inductances, determined by this equaitos, and as shown in the circuit like this… Further we have controlled vector potential current sources, determined by this equaiton, where the I hat is the vector potential current source, and I is electrical current. It is shown in the circuit like this… Also we have this controlled voltage sources, defternined by this equation, and as shown in circuit like this. Note an unit inductance is sued to account for time derivative here.(point on eqauion…)

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**VPEC Circuit Model VPEC model for two filaments**

Vector Potential Current Source VPEC model for two filaments Here is the two staring equation, by aobve basiss we obatin the folwlong vpec circuit eqations. Let’s give an example of vpec circuit model Of two filaments to illustrate the inside circuit element. First note that the wire rsitances and cpacirtance are still the same in peec model. we use effective resitances to account for the effect inductances, determined by this equaitos, and as shown in the circuit like this… Further we have controlled vector potential current sources, determined by this equaiton, where the I hat is the vector potential current source, and I is electrical current. It is shown in the circuit like this… Also we have this controlled voltage sources, defternined by this equation, and as shown in circuit like this. Note an unit inductance is sued to account for time derivative here.(point on eqauion…)

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**VPEC Circuit Model VPEC model for two filaments**

Vector Potential Voltage Source VPEC model for two filaments Here is the two staring equation, by aobve basiss we obatin the folwlong vpec circuit eqations. Let’s give an example of vpec circuit model Of two filaments to illustrate the inside circuit element. First note that the wire rsitances and cpacirtance are still the same in peec model. we use effective resitances to account for the effect inductances, determined by this equaitos, and as shown in the circuit like this… Further we have controlled vector potential current sources, determined by this equaiton, where the I hat is the vector potential current source, and I is electrical current. It is shown in the circuit like this… Also we have this controlled voltage sources, defternined by this equation, and as shown in circuit like this. Note an unit inductance is sued to account for time derivative here.(point on eqauion…)

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**Recap of VPEC Circuit Model**

Inherit resistances and capacitances from PEEC Inductances are modeled by: Effective resistances Controlled current/voltage sources Unit self-inductance Much fewer reactive elements leads to faster SPICE simulation Note that right now we have much less reactive elements, and as shown in the experiement it converges faster than peec model During spice simulation

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**Comparison with Localized VPEC**

Our solution Solution in localized VPEC [Pacelli:ICCAD’02] (1) It is not accurate to consider only adjacent filaments (2) There is no efficient and closed-form formula solution to calculate effective resistances

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**Introduction of G-Element**

Based

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**Closed-form Formula for Effective Resistance**

System equation based on G-element System equation based on K-element i.e. Major computing effort is inversion of inductance matrix LU/Cholesky factorization GMRES/GCR iteration (with volume decomposition) Inversion Based VPEC

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**Interconnect Analysis Based on VPEC**

PEEC (R,L,C) L^(-1) Full VPEC Sparsified VPEC SPICE Simulation Calculate PEEC elements via either formula or FastHenry/FastCap Invert L matrix 3. Generate full VPEC including effective resistances, current and voltage sources. 4. Sparsify full VPEC using numerical or geometrical truncations Directly simulate in SPICE

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**Spice Waveform Comparison**

Full PEEC vs. full VPEC vs. localized VPEC Full VPEC is as accurate as Full PEEC Localized VPEC model is not accurate

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Spiral Inductor Non-bus Structure: Three-turn single layer on-chip spiral inductor Full VPEC model is accurate and can be applied for general layout

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**Outline Introduction Vector Potential Equivalent Circuit Model**

VPEC Property and Sparsification Conclusions and Future Work

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**Property of VPEC Circuit Matrix**

Main Theorem The circuit matrix is strictly diagonal-dominant and positive-definite Sketch proof: Corollary The VPEC model is still passive after truncation

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**Numerical Sparsification**

Drop off-diagonal elements with ratio below the threshold Larger effective resistors are less sensitive to current change Calculate the ratio between off-diagonal elements and the diagonal element of every row Given the full matrix Example: truncation of 5-bit bus with threshold 0.09

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**Truncation Threshold 128-bit bus with one segment per line**

Models and Settings (threshold) No. of Elements Run-time (s) Average Volt. Diff. (V) Standard Dev. (V) Full PEEC 8256 281.02 0V Full VPEC 36.40 -1.64e-6V 3.41e-4V Truncated VPEC (5e-5) 7482 30.89 4.64e-6V 4.97e-4V Truncated VPEC (1e-4) 5392 19.55 1.29e-5V 1.37e-3V Truncated VPEC (5e-4) 2517 8.35 3.77e-4V 5.20e-3V Supply voltage is 1V VPEC runtime includes the LU inversion Full VPEC model is as accurate as full PEEC model but yet faster Increased truncation ratio leads to reduced runtime and accuracy

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**Waveforms Comparison Full VPEC is as accurate as full PEEC**

Sparsified VPEC has high accuracy for up to 35.7% sparsification

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**Geometry Based Sparsification - Windowed**

For the geometry of aligned bus line Windowed VPEC neighbor-window (nix , niy ) for aligned coupling and forwarded coupling consider only forward coupling of same wire

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**Geometry Based Sparsification - Normalized**

Normalized VPEC normalized aligned coupling n: segments number

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**Geometrical Sparsification Results**

32-bit bus with 8 segment per line Models and Settings No. of Elements Run Time (s) Avg. Volt. Diff. (V) Standard Dev. (V) Full PEEC 32896 Full VPEC (32, 8) 772.89 1.00e-5 6.26e-4 Windowed (32, 2) 11392 311.22 5.97e-5 1.84e-3 Windowed (16, 2) 3488 152.57 -1.23e-4 4.56e-3 Windowed (8, 2) 2240 85.14 -2.17e-4 8.91e-3 Normalized 4224 255.36 -6.05e-4 2.96e-3 Decreased window size leads to reduced runtime and accuracy Windowed VPEC has high accuracy for window size as small as (16,2) Normalized model is still efficient with bounded error

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**Runtime Scaling Circuit: one segment per line for buses**

The runtime grows much faster for full PEEC than for full VPEC full PEEC is 47x faster for 256-bit bus due to reduced number of reactive elements Sparsified VPEC reduces runtime by 1000x with bounded error for large scale interconnects

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**Conclusions and Future Work**

Derived inversion based VPEC from first principle Shown that Full VPEC has the same accuracy as full PEEC but faster Proved that VPEC model remains passive after truncation To work on Fast iteration algorithms for inversion of L Model-order-reduction for VPEC (see ICCAD’2006)

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