1. Design of Sub-mW RF CMOS Low-Noise Amplifiers
Derek Ho
Dept. of Electrical and Computer Engineering
University of British Columbia
March 30, 2007

2. Outline Motivation and Objectives Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work

3. Introduction What is an LNA?
A circuit used to provide gain where preserving the signal-to-noise ratio is important
Where can I find one?
In wireless/wireline receivers and sensor interfaces
Why ultra-low-power?
Want a long battery life for portable/remote applications and implants

4. (for data rate and range)
LNA Requirements
Receive Chain 2 3 4 1
Noise figure of receiver (F = noise figure, G = gain):
Ideally low
(for data rate and range)

5. LNA Requirements Output Input
Ideal
Better Linearity
Worse Linearity
Input
An LNA with good linearity can handle a larger input signal without deviating from linear operation.

6. LNA Design Challenges

7. Research Objectives
Devise a simple methodology that leads to power-efficient LNA designs
- Form a graphical toolkit to help reduce design time and improve design quality
- Explore LNA power-performance tradeoffs
- Find a low-voltage low-power circuit topology
- Demonstrate a high performance design in a deep submicron technology

8. Outline Motivation and Objectives Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work

9. Gain and Transconductance
Advantage of graphical approach: Quicker, more accurate
“gain / frequency response vs. bias”
“gain vs. bias”
(20/0.1), (40/0.1)
moderate inversion
moderate inversion
strong inversion
strong inversion
subthreshold
subthreshold
gm [mS]
fT [GHz]
(40/0.2)
VGS [V]
VGS [V]
Both fT and gm are strong functions of VGS
fT a strong function of L, but largely independent of W
MOSFET has poor subthreshold performance

10. Transconductance Efficiency gm/ID
moderate inversion
strong inversion
subthreshold
gm/ID [1/V]
VGS [V]
First proposed in 1996 for op-amp (low-frequency) design [1]
Represents “gain achieved” per unit “power consumed”
Decreases towards strong inversion
Insensitive to W and L
 can first design VGS (bias) then design W (size)

11. moderate
inversion
Linearity
strong inversion
subthreshold
VGS [V]
VIP3 of a 40nm nFET vs. VGS (VTH = 0.23V) [22]
VIP3 (measure of linearity, the greater the better) is the highest at moderate inversion (around 0.25V for the 45nm FET).

12. Outline Motivation and Objectives Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work

13. Circuit Topology Cascode Common-Source Cascode Design:
Lg, Ls, Ld, Cm, Ctune,
VB, VGS1, W1/L1, W2/L2
Problems with common-source
- Low device output resistance  low gain
- Poor input/output isolation  Instability

14. Transistor Sizing for Noise
Cascode
Common-Source
NFLNA [dB]
W [μm]
NF of LNA improves with larger W
However, power proportional to W
 Noise-power tradeoff

15. Design Procedure Step 1: Choose the bias VGS Selection criteria:
Design Sweet Spot
Step 1: Choose the bias VGS
Selection criteria:
Tradeoff gm (gain) and gm/ID (power)
For noise, want low VGS for a large W but avoid subthreshold operation
For linearity, exploit high VIP3
 Bias the device in moderate inversion gm
gm/ID

16. Design Procedure Step 2: Calculate ID
ID = (Power) / (Supply voltage)
Step 3: Transistor Sizing (Find W)
Step 4: Find gm
gm=d(ID)/d(VGS), or by simulation

17. Design Procedure Step 5: Determine gate-source cap Cgs
Decide whether adding Cm is beneficial Cm decreases fT but alleviate the need to build large inductors
Cgs = Cm || Cgs1

18. Design Procedure Step 6: Impedance matching
Design Lg, Ls, & Cm to create a 50Ω input impedance.
Small-signal model
Designing

19. Design Procedure Step 7: Design the load Ld and Ctune
Ld, Ctune and the parasitic caps at the output should resonate at the frequency of operation
Ld is often chosen as large as it can practically be implemented to increase gain
Designing

20. Outline Motivation and Objectives Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work

21. A 90nm 2.4GHz LNA Cascode with on-chip inductors
1V supply  can share with digital
We now proceed to LNA (circuit-level) design…

22. Gain “gain vs. bias” “gain vs. size” Av [dB] Av [dB] Power Power
VGS [V]
W [μm]
Gain insensitive to VGS
Gain does not scale well with W

23. Noise NF vs. f (sweeping VGS) Noise Summary
Power
Increase
VGS V: -0.6dB at 6.4x power
40% of total noise
(76% of which comes from the R’s in the inductors)
NF vs. f (sweeping W)
Power
Increase
Meaning: Need to make inductors with low series resistance!
W 10-40μW: -3.4dB at 4.2x power

24. Linearity Linkage between LNA performance and device characteristic
“LNA linearity vs. bias”
Power
IIP3 [dBm]
VGS [V]
40nm
Linkage between LNA performance and device characteristic

25. Summary of LNA Performance
Simulation Results
2.4 GHz
TABLE 2
Summary of LNA Performance
Gain: 22.7dB
Gain (dB)
22.7
NF (dB)
2.8
S11 (dB)
−14.7
IIP3 (dBm)
5.14
P1dB (dBm)
−10
PDC (μW)
943
fc (GHz)
2.4
Gate L (μm)
0.09
Power: 943μW
Noise: 2.8dB

26. Component Values
VDD (V) 1
Lg = Ld (nH) 5
Ls (nH) 2
Cm (fF)
480
Ctune (fF)
720
W1/L1 (μm)
25/0.1
W2/L2 (μm)
Vin,DC (V)
0.4
VB (V)
0.9
All components can be conveniently implemented on-chip!

27. Performance Comparison
> 1mW
< 1mW
This work (simulated) vs. others (measured)
This work focuses on design methodology
Highest gain amongst all LNAs
Good noise figure amongst sub-mW LNAs

28. Outline Motivation and Objectives Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work

29. Conclusion
A design methodology was devised for sub-mW RF CMOS LNAs having the following benefits:
1) simple to apply
2) can serve as a starting point for local optimization
3) based on the fundamental device properties
The gm/ID approached previously used for low-frequency op-amp design was adopted for radio-frequency design
A 2.4GHz 943μW LNA was designed with only manual design optimization

30. Future Work Enhancements to the proposed methodology:
Incorporate a quantitative noise analysis into the gm/ID design framework
Account for process variation and DFM concepts
Silicon verification
Interesting/high-impact research areas:
Noise optimization technique for the ultra-low-power design space
Further exploitation of high FET linearity in moderate inversion

31. Related Publications
D. Ho and S. Mirabbasi, “Design considerations for Sub-mW CMOS RF low-noise amplifiers,” to appear in IEEE Canadian Conference on Electrical and Computer Engineering, 2007.
D. Ho and S. Mirabbasi, “Low-voltage low-power low-noise amplifier for wireless sensor networks,” IEEE Canadian Conference on Electrical and Computer Engineering, 2006.

32. References
[1] F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE J. Solid-State Circuits, vol. 31, no. 9, Sep
[2] T.-K. Nguyen, S.-K. Han, and S.-G. Lee, “Ultra-low-power 2.4GHz image-rejection low-noise amplifier,” Electronics Letters, vol. 41, no. 15, July 2005.
[3] D. B. G. Perumana, S. Chakraborty, C.-H. Lee, and J. Laskar, “A fully monolithic 260-μW, 1-GHz subthreshold low noise amplifier,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 6, Jun 2005.
[22] Ming Cai, “Design studies of nanometer-gate low-noise amplifier near the limits of CMOS scaling,” Doctor of Philosophy Thesis, University of California, San Diego, San Diego, CA, 2006.
[28] S. B. T. Wang, A. M. Niknejad, and R. W. Brodersen, “Design of a sub-mW 960-MHz UWB CMOS LNA,” IEEE J. Solid-State Circuits, vol. 41, no. 11, Nov
[29] D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P. Wambacq, S. Donnay, and S. Decoutere, “Low-power 5 GHz LNA and VCO in 90nm RF CMOS,” IEEE Sym. on VLSI Circuits, June 2004.
[30] S. Asgaran, M. J. Deen, and C.-H. Chen, “A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance used for input matching,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 4, Apr
[31] L.-H. Lu, H.-H. Hsieh, and Y.-S. Wang, “A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 10, Oct
[32] T.-S. Kim and B.-S. Kim, “Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker,” IEEE Microwave and Wireless Component Letters, vol. 16, no. 4, Apr
[33] M. Shouxian, M. Jian-Guo, Y. K. Seng, and D. M. Anh, “A modified architecture used for input matching in CMOS low-noise amplifiers,” IEEE Trans. on Circuits and Systems II, vol. 52, no. 11, Nov

33. Thank you!

34. Appendices

35. I-V Characteristics (90nm nFET)
VGS = 0.7V
1mW
VGS = 0.6V
ID [mA]
0.5mW
VGS = 0.5V
0.1mW
VGS = 0.4V
VGS = 0.3V
VDS [V]
ID scales with W, ID does not scale with 1/L
Bias selection with constant power contours

36. Characteristic Current Densities
S.P. Voinigescu, T.O. Dickson, T. Chalvatzis1, A. Hazneci, E. Laskin, R. Beerkens, and I. Khalid, “Algorithmic Design Methodologies and Design Porting of Wireline Transceiver IC Building Blocks Between Technology Nodes,” CICC, San Diego, Sept.19, 2005.

37. Drain Current Modeling
90nm FET
Square Law
DSM
Actual

38. Linearity – IP3 Intermodulation Distortion
By Quasi Periodic Steady State (QPSS) Analysis

39. Dynamic Range – P1dB
1dB compression point by Periodic Steady State (PSS) Analysis