1. AMD OpteronTM Overview

2. Top Level Agenda The HPC Market & AMD AMD64 – A Programmers View
AMD Opteron Processor – The HW
Core Improvements
Integrated Memory Controller
HyperTransport Technology Clustering Performance
System Solutions & Applications
Development platforms
Recent Events
Summary
April 16, 2017
Computation Products Group

3. Computing System Evolution: Mainframes to desktops to clusters
Tightly coupled processor, computer, OS and software from a single company
Proprietary software
>$1M
Departmental Minicomputers ~ 1970
Significant proliferation of servers as machines leave glass houses
<$1M
RISC Processors ~1982
The beginning of “Commodity Computer Market”
Processor, Computer and Software begin to un-bundle
A proliferation of new companies (SUN, MIPS, SGI) with the promise of significantly improved performance
Desktop ~ 1985
Commodity market takes hold - IBM and Apple emerge as market leaders
Cluster HPC ~ 1992 Onwards
Gradual and steady growth of clustered systems for HPC
April 16, 2017
Computation Products Group

4. Enterprises want legacy compatibility
IDC's Worldwide Quarterly Server Forecast- 12/12/02
14%
Red = Total Market Growth
Black = IA32 Growth
April 22, 2003
14%
15%
14%
11%
-2% 5%
15%
Target market for
AMD Opteron™
processor*
15%
10% 1% 5%
x86 currently dominates the volume of servers in the enterprise – 90% in For the next several years, IDC forecasts that x86 will remain the accepted enterprise server platform, while other proprietary platforms attain only niche status in the marketplace.
Proprietary 64-bit platforms such as Itanium and Sparc have challenges in running 32-bit applications and will continue to be limited to niche acceptance.
This forecast suggests that enterprises are painfully aware of the costs of disruption, and that they demand legacy compatibility - which is why AMD believes that the AMD Opteron will soon become the choice for enterprises.
The growth in today’s server market is toward technology based on the x86 platform.
Competing 64-bit products are niche, proprietary technologies that are expensive and difficult to integrate with existing systems.
*Based on AMD market trend research
April 16, 2017
Computation Products Group

5. HPC Projected Market Breakout
What will happens to processor distribution in the next three years?
HPC market will continue to grow >12%/yr
Alpha & PA-RISC represent 32% of TAM -> 0%
SGI and SPARC are losing market share
Intel and AMD are focused on the prize
32% + 10% x = 42% up for grabs
~3M processor over the next three years
2005 >$10B
2002 $7B
IDC predicts the overall HPC market to grow 12% from 2002 to 2005 – from $7B to $10B.
There is a significant opportunity for Opteron to capture a high percentage of this business:
Alpha, PA-RISC are going EOL to Itanium2.
Itanium2 does have good floating point and will have some market share.
In the HPC market, Opteron should win in:
Price,
Price/Performance
Integer performance
Density (lower power)
Ease of migration with native 32-bit x86 application support
3 years
Alpha
PA-RISC
April 16, 2017
Computation Products Group

6. Evolving Server Market
“… open source platforms and mass commoditization, will drive the server market through the next decade” *
Standards-based, volume-driven, low-cost solutions
Enhanced computing resources with support for legacy applications
Improved return on investment (ROI)
Examples:
Windows NT/2000 leading the field with more than 55% share in the SMB segment **
Migration away from Precision Architecture (PA)-RISC and Alpha™ Processors and toward x86-based systems
Revenue dollars for RISC-based servers are expected to be eclipsed by other computing platforms for the first time in 2002
The industry looking for:
Standards based, volume driven low cost…..
Enhanced computing resources with support for legacy applications
Improved return on investment (ROI)
Examples of this trend:
Windows NT/2000
Migration from Precision Architecture….
Revenue dollars for RISC based
* Source IDC 2000
** Source IDC, 2002
April 16, 2017
Computation Products Group

7. AMD Server Successes Key AMD OpteronTM processor milestones
February 2002 – First public demonstrations of upcoming
AMD Opteron™ processor, running in 32-bit mode.
March 2002 – SuSE Linux AG announces its Linux OS will offer full 64-bit support for AMD's family of 64-bit processors.
April 2002 – AMD announces the AMD Opteron processor brand for multiprocessor workstations and servers.
April Microsoft
announces intent to incorporate 64-bit support for AMD Athlon™ and
AMD Opteron processors.
June 2002 – AMD demos first 4-way AMD Opteron processor-based server at Computex.
July 2002 – IBM announces 64-bit enablement of the DB2 database software for the upcoming
AMD Opteron processors.
This slide presents a quick overview of some industry leaders that have publicly stated their support for the AMD64 platform.
All major operating systems vendors are expected to support the AMD 64-bit architecture including Microsoft, RedHat, SuSE, United Linux (comprised of SuSE, Conectiva, Caldera and TurboLinux), MandrakeSoft and Wasabi. At the time of launch, we expect full 64-bit support for the upcoming AMD Opteron and AMD Athlon 64 processors from Linux and full 32-bit support on Microsoft Windows.
AMD is working with all current software partners as well as many new ones to provide the application packages our customers require. Many major enterprise software application providers have also demonstrated support for the upcoming AMD Opteron processor including Oracle 9i, Tivoli, Covalent and Sendmail. A complete list of software partners and available software products will be announced at launch.
August 2002 – Red Hat announces it will offer global support for the upcoming AMD Opteron and AMD Athlon processors.
October 2002 – Cray and Sandia National Labs announce plans to build “Red Storm,” a massive parallel processing supercomputer with >10,000 AMD Opteron processors.
January 2003 – IBM announces beta availability of DB2 for
AMD Opteron processors.
April 16, 2017
Computation Products Group

8. AMD Athlon™ processors in use…
Rhythm & Hues employed 42 dual processor-based Angstrom Microsystems servers running AMD Athlon™ processors in its render farm.
Pre-visualization by JAK Films and post-production by Industrial Light & Magic
used systems powered by
AMD Athlon™ MP processors. Used in Star Wars – Episode II
Boeing selected AMD processors to power a 96-node AMD Athlon™ super-cluster to support its Delta IV program. Cluster used to simulate aerodynamic performance of rocket family.
AMD Athlon™ MP processors power creativity in Spy Kids 2: The Island of Lost Dreams
Electronic Arts to use AMD Athlon™ processor-based systems worldwide
Mercedes-Benz Technology Center (MTC) in Germany utilizes a cluster based on AMD Athlon processors to do crash simulation analysis on its vehicles.
Veritas Geophysical is processing high-resolution seismic data with AMD Athlon™ processor-based Racksaver Cluster that provides an incredible amount of computing power under one roof.
April 16, 2017
Computation Products Group

9. Heidelberg University
Some of the most powerful computers in the world today – driven by AMD!
Top 500 Supercomputing List (as of November 2002)
UMEA University HPC2N Super Cluster
68h with 480 processor system running AMD Athlon processors
124th with 120 dual processors nodes running AMD Athlon processors
215rd with 264 processor Racksaver system running AMD Athlon processors
University of Bochum
302nd – MegWare System with 128 AMD Athlon processors
University of Vienna
304th – Helix, a Megware system with 132 AMD Athlon processors
370th – Schroedinger I, a self-made system with 160 AMD Athlon processors
Heidelberg University
139th – Prairiefire, a Atipa Technology system with 246 AMD Athlon processors
64th with 256 dual processor nodes running AMD Athlon processors
April 16, 2017
Computation Products Group

10. The AMD Opteron™ processor Project “Red Storm”
Cray will build a 40+ teraflop super computer using x86-64 AMD Opteron™ processors for Sandia National Laboratories
Will be used for advanced engineering simulations
$90 million project will use more than 10,000 AMD Opteron™ processors
Will feature a simple building block approach with HyperTransport™ technology that will enable easy implementation and reduce engineering, design, and component costs
RED STORM
April 16, 2017
Computation Products Group

11. Programmers Point of View

12. x86 in High Performance Computing - The Six System Challenges
#6: Watt density:
With clusters exceeding 10,000 processors, watt density is an important issue. As cluster size expands, cooling capacity and costs can be significant.
Design the lowest watts/Gig Cycle solution leveraging start-of-the-art AMD64 architecture and silicon on insulator process
x86 is the most widely installed instruction set in the world.
Instruction set not relevant to CPU performance (“to first order”).
What is important:
#5: The I/O infrastructure:
The bandwidth of a Front Side Bus causes an I/O bottle-neck which continues to exclude IA32 from running challenging parallel applications.
Provide a dedicated I/O buss which is separate from the memory bus and keeps pace with next generation I/O protocols and CPU clock.
#4: Addressable memory:
Large RAM resident databases and memory intensive applications exceed the 4 Giga-Bytes limit of 32 bit systems. Paging is not a solution.
AMD64 processing is the only real solution
#3: Memory bandwidth:
With increased system memory, come data intensive applications with strides and block sizes that cause cache thrashing. Making the cache larger is not cost effective. Hence, performance is limited by the size of on chip cache and/or memory bandwidth.
Improve memory bandwidth and latency – limit cache size $$$
#2: Cost per processing node:
Due to cost / performance and I/O constraints, IA32 clusters are limited to two (2) processors putting additional stress on SMP cluster interconnect
Bring 4 and 8 processor SMP systems closer in cost/performance to 2 processor systems;
Improve performance, decrease premium…without breaking IA32 “commodity” economics;
Only possible - if the same processor architecture is used on the desktop.
#1: Backward compatible to x86-32:
There is a enormous investment is IA32 for all market segments. In many applications, porting code is not an option.
Provide a solution that is not only 100% backwards compatible, but designed to run IA32 code faster then any existing 32-bit architecture available.
Provide a gradual and controlled migration path for porting to AMD64
Make the total cost of ownership minimal.
April 16, 2017
Computation Products Group

13. AMD’s Solution is an Evolutionary Approach: Backward compatible to IA32
AMD: Single Platform
Designed to maintain legacy compatibility …
Leverage existing infrastructure – thermal, enclosures, power, and BIOS
Run existing 32-bit applications natively
Allow customers to migrate according to their schedule
Low learning curve for users and support staff
(< 3GB Limit)
(4GB Limit)
Single IT infrastructure:
Single platform that provides:
32 bit apps on 32 bit OS
32 bit apps on 64 bit OS
64 bit apps on 64 bit OS
All industry leading performance
All industry leading price/performance value - will blow the competition away
Obeys the “Immutable Laws”
A Hammer-based system (Athlon/Opteron) is a high performance platform for both 32-bit AND 64-bit applications. Prior to Hammer, users had to choose between 32-bit systems or 64-bit systems or a 64-bit platform that could only runs 32-bit applications in emulation mode (IA-64).
Athlon/Opteron systems provide an environment where each 32-bit application can be enabled to have access to 4GB of memory. Currently, in the x86 environment, all software running on a computer must share memory, which is limited to 4GB since this is the addressable limit of 32-bit computing.
Athlon/Opteron systems are based on the x86-64 instruction set, which provides a direct migration path to 64-bit computing. Only two new commands have been added to x86-64, meaning that ISVs do not have to re-architect their entire application to move to a 64-bit version.
… and obey the Immutable Laws.
April 16, 2017
Computation Products Group

14. Compatibility Thunking Layer
64-bit Process
64-bit Process
IA32 Application
AMD64 Application
Thunking Layer
USER
KERNEL
Thunking is a term used to describe calling cross platform code and can mean calling 32 or 16bit code from a 64bit platform or calling 64bit code from a 32bit platform.  In essence, a thunk is a translation layer that sits between the 32bit application and the 64bit process code.  
There are two basic methods used for thunking, which is a function of the calling platform.  In the case of 32bit application calling 64bit application, the generic thunking functions in the 64bit kernel can be used.  For the opposite scenario, the 64bit process must use a flat thunk to get the job done.  It is also worth noting that flat thunks can be used to make 32bit to 64bit calls but because flat thunks are far more difficult, generic thunks are preferred for this situation.
AMD64 Operating System
AMD64 Device Drivers
April 16, 2017
Computation Products Group

15. Compatibility Mode Compatibility Mode
Provides a mode where existing IA32 applications can run unchanged under a 64-bit OS (Long Mode)
Selected on a code-segment basis (CS.L=0)
Uses far transfer rather than a full mode switch
Faster than mode switch
Application-level code runs unchanged
Legacy segmentation
Legacy address and data size defaults
System aspects use native 64-bit mode semantics
Interrupts and exceptions use Long Mode handling
Paging aspects use Long Mode semantics
Compatibility Mode 15 31
Selector
Effective Address
Segmentation 63 31
Virtual Address
Paging 39
Opteron’s Physical Address
April 16, 2017
Computation Products Group

16. 64-bit mode
64-bit mode presents a flat, un-segmented virtual address space
The legacy x86 segmentation scheme is disabled in 64-bit mode
Default data size is 32 bits
Override to 64 bits using new REX prefix
Override to 16 bits using legacy operation size prefix (66h)
Default address size is 64 bits
Pointers are 64 bits
Switch between 64-bit mode and Compatibility Mode accomplished via normal Far Transfer instructions
CALLF, RETF, JMPF, IRET, INT
64-bit Mode 63
Virtual (Linear) Address
Paging 39
Opteron’s Physical Address
April 16, 2017
Computation Products Group

17. Register Extension http://www.x86-64.org SSE x87 GPR AMD64
64-bit integer registers
40-bit Physical Address
48-bit Virtual Address
Register Extensions
Sixteen 64-bit integer registers
Sixteen 128-bit SSE registers
Vector Math Instruction Set
3DNow!™
SSE & SSE2 support
Done in such a way as to not alter the IA32 instruction set.
RAX 63 31 AH
EAX AL 7 15
In x86
Added by x86-64
XMM0
SSE
127
XMM7
x87 79
GPR
EAX
EDI
XMM8
XMM15 R8
R15
EIP
April 16, 2017
Computation Products Group

18. REX (Register Extension)
The sweet spot is 8 to 15 registers - 90% of application need <15
April 16, 2017
Computation Products Group

19. AMD OpteronTM Processor Ecosystem Operating Systems
Type
Available
Comments
Windows 2000 Server editions
32-bit 
Users will need to get Opteron chipset drivers from AMD
Red Hat Professional 8.0
SuSE Linux 8.1 editions
Solaris 9 for x86
UnitedLinux Version 1
64-bit
Consortium includes SuSE, The SCO Group, Conectiva, Turbolinux
Linux 2.4 kernel patches
Mandrake Linux Corporate Server 2.1
64- bit
4/22/03
SuSE Linux Enterprise Server (SLES) 8
Beta available from AMD for OEMs, ISVs, and IHVs
Windows Server 2003
4/24/03
NetBSD
Development underway by Open Source community
Beowulf Sycld Operating System
Linux-based cluster operating system
Turbolinux
RC1 candidate available at launch
Red Hat Advanced Server 3.0
Stay Tuned
Support announced 08/02 but no release schedule announced.
Windows for AMD64
Pre-alpha available from Microsoft for OEMs, ISVs, IHVs at
FreeBSD, OPENBSD
Development underway by Open Source community.
April 16, 2017
Computation Products Group

20. AMD OpteronTM Processor Ecosystem Open Source Development Tools
64-bit Tools
Type
Available
Comments
ATLAS Developer Release
Library 
Optimized BLAS (Basic Linear Algebra Subroutines) library
Blackdown Java Platform 2 Version 1.4.2
Linux JAVA
SUN Java products ported to Linux by Blackdown group
GNU binutils
Utilities
GNU collection of binary tools including GNU linker, GNU assembler
GNU C++ (g++) 3.2
GNU C (gcc) 3.2
GNU C (gcc) 3.3 (optimized)
Compilers
GNU Collection of Compilers (gcc) is a full-featured ANSI C compiler
GNU Debugger (GDB)
Debugger
Analysis tool for debugging programs - included with SuSE SLES 8
GNU glibc 2.2.5
GNU glibc (optimized)
C Library
GNU C Library
Other GNU Tools
Various
bash, csb, ksb, strace, libtool - included with SuSE SLES 8
MPICH
Open Source message passing interface for Linux clusters
PERL, Python, Ruby, Tcl/Tk
Language
Scripting languages - included with SuSE SLES 8
GNU means GNU's Not UNIXTM" and is the primary project of by the Free Software Foundation (FSF), a non-profit organization committed to the creation of a large body of useful, free, source-code-available software.
April 16, 2017
Computation Products Group

21. AMD OpteronTM Processor Ecosystem ISV Development Tools
AMD64 Tools
Type
Available
Comments
64Express
Code Migrator 
Source code migration technology for windows and Linux by MigraTEC
RSA
Library
Encryption library available from RSA Securities
SoftICE beta 1
Debugger
Windows device driver debugger by CompuWare
PGI Workstation 5.0 beta
Optimized Compilers
to download
FORTRAN 77/90, C, C++ compilers for 64-bit Linux
4/14/03
to download
FORTRAN 77/90, C, C++ compilers for 32-bit Linux, Windows
AMD Core Math Libraries (ACML)
Optimized Libraries
4/22/03
Linux
Optimized numerical functions (BLAS, LINPACK, FFTs) for Linux and Windows ported by NAG. Will be downloadable from AMD web site.
PGI Workstation 5.0 Production Release
Toolkit
06/03
Optimized FORTRAN 77/90, C, C++ compilers for 64-bit Linux, 32-bit Linux, and 32-bit Windows; PGDBG parallel application debugger; PGPROF parallel application performance profiler
PGI Cluster Development Kit (CDK) 5.0
07/03
Toolkit that includes optimized FORTRAN 77/90, C, C++ compilers for 32-bit and 64-bit Linux plus tools for cluster application development.
TotalView
Stay tuned
Etnus has announced 32-bit support. 64-bit discussions underway.
Vampir/Vampirtrace
Analysis
Parallel performance analysis tool by Pallas GmbH
Visual C, C++
Compiler
Windows compiler included in Windows for AMD64 pre-alpha
Distributed Debugging Tool
Streaming Computing has announced support 64-bit graphical debugger for AMD64
Vega Prime
3D App Dev
Realtime 3D software tools by Multi-gen Paradyn.
Absoft
Compilers
Fortran toolsets for Windows and Linux
April 16, 2017
Computation Products Group

22. AMD OpteronTM Processor Ecosystem Server Applications
64-bit Applications
Type
Available
Comments
Apache HTTP Server
Web Server 
- open source
Mental Ray by Mental Images
Rendering Engine
Packaged with graphic front ends
Zeus by Zeus
Cluster Strike Server by Valve
Gaming Server
SENDMail
Server
4/22/03
- open source
MY SQL
Database Engine
Open source
DB2 by IBM
Q302
Beta available from IBM
Apache Server by Covalent
Stay tuned
Support announced 10/02
Stronghold by Red Hat
Ingres by CA
Technology demo shown 01/03
Unicenter by CA
Management
Oracle
Technology demo shown 10/02 and 01/03
MS IIS by Microsoft
Available with Windows for AMD64 pre-alpha
Terminal Server by Microsoft
Transaction Server
MS SQL
Database Server
In early development
Engage with ISVs, Open Source Community, and corporate developers to port applications that immediately benefit from 64-bit computing to AMD64
April 16, 2017
Computation Products Group
Software listed in alphabetic order

23. AMD OpteronTM Processor Ecosystem Additional Target Applications
Type of Application
Vendor
Application Servers
BEA, IBM
Business Processing Applications
JD Edwards, Oracle, PeopleSoft, SAP, Siebel
Java Engines (JVMs)
BEA, IBM, SUN
HPC Applications
Abaqus, Ansys, Fluent, LS-DYNA, Landmark, NASTRAN
Messaging/Collaborative Engines
Lotus Domino, MS Exchange
Streaming Media Engines
Microsoft, Real Networks
Statistical Engines
SAS
Transaction Engines
Citrix
Workstation Software
Adobe, Alias/Wavefront, Autodesk, Avid, Discreet, Softimage, Solid Works
Engage with ISVs, Open Source Community, and corporate developers to migrate applications to AMD64
April 16, 2017
Computation Products Group

24. AMD OpteronTM Processor Ecosystem Infrastructure Target Applications
Type of Application
Vendors/Application
BIOS
Phoenix, AMI
Diagnostics
AMI, UltrX, Eurosoft, PC-Doctor
Management
Altiris, BMC, CA, HP, Tivoli, NetIQ, Novell ZenWorks, OSA
Security/Antivirus
CA eTrust, Symantec
Storage Management
Legato, PowerQuest, Veritas
Utilities
Symantec Norton Utilities
Virtualization
Connectix, VMWare GSX
Engage with ISVs to valid 32-bit applications and to migrate applications to AMD64 when it makes sense
April 16, 2017
Computation Products Group

25. AMD OpteronTM Processor Ecosystem SLES 8 for AMD64 Features
Web Server
Apache web server with extensions
PHP and PHP extensions
Tomcat
Network Printing
CUPS, lprng
Internet/Intranet Services
DNS (bind)
WINS
DHCP server and client
FTP, TFTP
Mail and News Servers
SMTP (postfix), POP, IMAP
Proxy Servers
Caching and filtering: squid
SQL Database Servers
mysql, postgres
Client support (ODBC, JDBC)
Standard Linux/UNIX shells
bash, csh, ksh
File Sharing
Windows: Samba 2.2.5
Macintosh: netatalk
Netework filesystems: NFS
Authentication Server
Windows domain controller: Samba
Directory service: LDAP
Single sign-on: Kerberos 5
Logon: PAM module
Yellow pages: NIS Server
Graphical Interfaces
KDE minimal system
Mozilla 1.0.1
KDE libraries
GNOME 2.0 libraries
Security
Secure shell: ssh
Secure sockets: Openssl
Encryption: GnuPG
Full crypto enabled
GPG signed RPM files
Firewall (iptables)
VPN: FreeSwan
Applications and infrastructure components included in SLES 8 for AMD64 launch release
April 16, 2017
Computation Products Group

26. AMD OpteronTM Processor Ecosystem SLES 8 for AMD64 Features
Tools
Description
Compilers
C (gcc) 3.2
C++ (cpp) 3.2
Scripting Languages
Perl, Python, Ruby, Tcl/Tk
Development Tools
diff, patch, make, lex (flex)
yacc (bison), autoconfig, automake
Binutils, libtool, GDB, strace
Archiving Tools
tar, cpio, gzip, bzip2, rpm
Libraries and Core Functionality
LSB 1.1 runtime environment
glib 2.2.5
Management Tools
YaST – graphical administration tool
AutoYasT – installation tool
Networking Tools
Remote shell tools: ssh, scp
ping, traceroute, nslookup, dig, host
IPv6: ifconfig/route and config location
Firewalling tools: ipchains, iptables, masquerading
Xfree (libs and server)
X print server (libx.P.so.6)
SNMP
Complete suite of open source development, networking, and management tools are included in SLES 8 for AMD64 launch release
April 16, 2017
Computation Products Group

27. The AMD Opteron™ Processor Ecosystem SuSE SLES 8 for AMD64 Features
Disk Adaptors
NICs and Interconnects
Video & Audio
Promise
FastTrack TX2000
FastTrack 100 TX2
FastTrack100
FastTrack SX6000
PDC20375
3Com
3C905CX
3c996
Gig Ethernet Adapter BCM 5703
Gig Ethernet Adapter BCM 5704
NVIDIA
GeForce4
GeForce4MX200
GeForce4MX 400
Quadro2
Quadro2 DCC
Quadro4
3Ware
7500-2/4/8/12
8500-4/8/12
Myricom (HPC Interconnect)
Myrinet Clustering Interconnect
ATI
FireGL X1
FireGL 8800
FireGL 8700
Adaptec
29320x
39320x
29160x
2200S series
2120S series
JNI (InifiniBand)
InfiniStar 4X HBA
Matrox
Parhelia 128
Parhelia Pro 256
Parhelia 512
LSI Logic
LSI22320/53C1030
MegaRAID SCSI 320-2
MegaRAID SCSI 320-1
LSI7202XP-LC
Qlogic (Fibre Channel)
SANblade 2310xx
SANblade 2340xx
SANblade 2342xx
Creative Labs
SB Audigy
SB Audigy2
SB Live! 5.1
SB Live! Cards
64-bit Linux Device Drivers included in SLES 8 for AMD64 launch release
April 16, 2017
Computation Products Group

28. BIOS There are four sources for BIOS for the AMD Opteron. They are:
Phoenix Technologies Jim Grimm Director of Sales NA 320 Norwood Park South Norwood, MA Phone: (781) Fax:
American Megatrends, Inc. Bill Clark Strategic Account Mngr F Northbelt Parkway Norcross, GA Phone: (770) Fax:
CodeGen T.J. Merritt Sales Manager 4725 First Street Pleasanton, CA Phone: (925) Fax:
AMD will release to the public on April 22, 2003, documentation that will enable the development of a open LinuxBIOS. In addition, SuSE has an engineering project underway to develop a LinuxBIOS for Opteron systems. The intent of this project is to deliver code to open source in a phased approach as different levels of functionality are achieved. All questions concerning this development effort need to be addressed to: Mr. Andreas Jaeger at SuSE
April 16, 2017
Computation Products Group

29. Linux for AMD64 What is Linux?
Linux is an open source operating system that is a Unix clone
Open Source refers to any software where both the executable (binary) files and source code are distributed.
The Linux concept originated from Minix, a Unix-like operating system used to teach the inner-workings of an OS to students
Linux was introduced over the Internet in 1991 by Linus Torvalds. In 1994 Linus merged together software components from hundreds of programmers to create Linux Version 1.0.
Linux distribution refers to a packaging of the Linux kernel (operating system core) with a set of utilities and other applications to make the OS user-friendly
Vendors providing Linux distributions charge fees for add-on features and services, such as media distributions, documentation, and support.
Linux Distributions that will support AMD64 on 4/22/03:
Mandrake Linux Corporate Server
NetBSD
Scyld Beowulf Linux
SuSE Linux Enterprise Server 8
Turbolinux
Linux was designed to be similar to Minix, a UNIX-like operating system used to teach students about the basics of operating system inner-workings. When the author of Minix refused to accept changes, Linus put out a proposal to create a completely new OS. Linux urged people to submit what they liked/didn’t like about Minix, “as the new operating system will resemble it somewhat.” In other words, Linux originated from Minix in concept, but not in code. Your description here is close enough; just want to make sure the distinction is clear from anyone trying to elaborate on that point as they talk through the slide.
Worthy of note: The utilities included in a Linux distribution aren’t technically part of the operating system. The operating system is the kernel. Most Linux distributions come with Unix utilities to give them a Unix look and feel, which also makes the interface familiar to people using Solaris, UnixWare, HP/UX, and other Unix operating systems. Embedded Linux (such as what AMD’s PCS division might use) may not contain any Unix utilities. They can use their own GUI application launchers and applications instead if they prefer, no command prompt nor Unix-like file system permissions needs to be in the distribution if they would be considered overkill.
April 16, 2017
Computation Products Group

30. Linux for AMD64 Linux Kernel for AMD64
Kernel refers to set of core operating system services that are tightly integrated with the processor, such as memory access, I/O functions, file services, and device drivers.
Linux Kernel for AMD64 was developed by AMD, SuSE, and the Open Source Community.
Linux Kernel for AMD64 is an Open Sources Software available for use by anyone. Any distribution of the binary version of this kernel must also be accompanied by source code version.
Kernel Features
Kernel
Raw device support for database
Async I/O, Direct I/O, Multipath I/O
POSIX Threads (linuxthreads)
PCI-X support
File systems: ext3, reiserfs, ext2
High Availability
Logical Volume Manager (LVM) for use with all supported file systems
April 16, 2017
Computation Products Group

31. Linux for AMD64 SLES 8 for AMD64 Features
Web Server
Apache web server with extensions
PHP and PHP extensions
Tomcat
Network Printing
CUPS, lprng
Internet/Intranet Services
DNS (bind)
WINS
DHCP server and client
FTP, TFTP
Mail and News Servers
SMTP (postfix), POP, IMAP
Proxy Servers
Caching and filtering: squid
SQL Database Servers
MySQL, PosgreSQL
Client support (ODBC, JDBC)
Java (JVM)
IBM 1.3.X (32-bit)
Backdown (64-bit)
Standard Linux/UNIX Shells
bash, csh, ksh
File Sharing
Windows: Samba 2.2.5
Macintosh: netatalk
Network file systems: NFS
Authentication Server
Windows domain controller: Samba
Directory service: LDAP
Single sign-on: Kerberos Heimdal 0.4e
Logon: Password Authentication Modules
Yellow pages: NIS Server
Graphical Interfaces
KDE minimal system
KDE libraries
Web Browsers
Mozilla 1.0.1
Konqueror
Security
Secure shell: ssh
Secure sockets: OpenSSL
Encryption: GnuPG
Full crypto enabled
GPG signed RPM files
Firewall (iptables)
VPN: FreeS/wan
Sample of some of the open source applications and utilities included in SuSE SLES 8 for AMD64
Not all-inclusive… there are many lesser-known programs distributed in distributions like SLES that perform similar functions. This list does cover the majority of features people would be looking for, though. 
April 16, 2017
Computation Products Group

32. Linux for AMD64 SLES 8 for AMD64 Features
Tools
Description
Compilers
C (gcc) 3.2
C (gcc) 3.3 (for better performance)
C++ (g++) 3.2
Scripting Languages
Perl, Python, Ruby, Tcl/Tk
Development Tools
diff, patch, make, lex (flex)
yacc (bison), autoconfig, automake
Binutils, libtool, GDB, strace
Archiving Tools
tar, cpio, gzip, bzip2, rpm
Libraries
glibc 2.2.5
glibc (for better performance)
Management Tools
YaST – graphical administration tool
AutoYaST – installation tool
Networking Tools
Remote shell tools: ssh, scp
ping, traceroute, nslookup, dig, host, ltrace
IPv6: ifconfig/route and config location
Firewalling tools: ipchains, iptables, masquerading
Xfree (libs and server)
X print server
SNMP
DHCP server (dhcpd)
Suite of open source development, networking, and management tools included in SuSE SLES 8 for AMD64
April 16, 2017
Computation Products Group

33. Linux for AMD64 SuSE SLES 8 for AMD64 Features
Disk Adaptors
Promise
FastTrack TX2000
FastTrack100
FasTrack100 TX
3Ware
7500-2/4/8/12
8500-4/8/12
Adaptec
29320x
39320x
29160x
2200S series
2120S series
LSI Logic
LSI22320/53C1030
MegaRAID SCSI 320-2
MegaRAID SCSI 320-1
LSI7202XP-LC
ATA (IDE) Drives
Support for many popular drives
NICs
3Com
3C905CX
3c996
Broadcom
5701
5702
5703
5704
Qlogic (Fibre Channel)
SANblade 2310xx
SANblade 2340xx
SANblade 2350xx
Intel
Pro100MT
Pro100
Miscellaneous
2D Graphic Cards
Support for many popular cards
Creative Labs (audio)
SB Live! 5.1
Printers
Support for many popular printers
Other I/O Devices
CD-RW
DVD-ROM
USB devices
PS/2 keyboards
Mouse: PS/2, serial
Some of the 64-bit Linux Device Drivers included in SLES 8 for AMD64 launch release
Note: High speed interconnect device drivers available from Dolphin, Myrinet, Quadrix
3D graphic card device drivers available from ATI, NVIDIA, Maxtor
April 16, 2017
Computation Products Group

34. Don’t take our word for it . . .
“Jim Allchin, the man in charge of Microsoft's operating systems, calls the performance of software on the AMD machines ‘pretty amazing.’"
Fortune Magazine, February 2003
“The enterprise-class database solution features a DB2 database on a SuSE Linux operating system, and was successfully enabled to support x86-64 technology in two days.”
AMD News Release, July 30, 2002
"AMD's x86-64 technology offers a seamless migration path to 64-bit computing, while allowing businesses to preserve their existing investments in 32-bit x86 software.” Boris Nalbach, CTO of SuSE Linux AG.
AMD/SuSE News Release, March 20, 2003
April 16, 2017
Computation Products Group

35. Don’t take our word for it . . .
Privately held computer seller Angstrom Microsystems will use Hammer to build high-performance servers for financial institutions, movie studios, and oil companies. The Boston company says customers were concerned that they would have to rewrite software for Itanium. "People want an evolutionary process, not a revolutionary process," says CEO Lalit Jain.
Business Week: AMD's Hammer: The Right Tool for the Job? (3/10/03)
“Covalent will be developing 64-bit compatibility because we believe the upcoming AMD Opteron processor-based server systems will deliver superior performance and reliability for our easy-to-install Apache server software.” Mark Douglas, senior vice president of engineering, Covalent Technologies.
AMD News Release,
April 16, 2017
Computation Products Group

36. AMD OpteronTM Software A Word on Architectural Feedback
Code size is only up about 5%
Mostly due to 64-bit literals
Instruction count is down about 15%
Additional registers really paying off
Many spill/fill memory references eliminated
Call-Exit sequences vastly improved
Reduced instruction count and increased Instructions Per Cycle (IPC) mean substantial performance gains
AMD Opteronä IPC improves about 5%
AMD64 instruction count down about 15%
Net improvement about 20%
Your mileage will vary
IA64 feedback is exactly opposite
Instruction count is up
IPC is down
April 16, 2017
Computation Products Group

37. Computing Strategy: x86-64
Legacy: 32-bit OS
Both AMD Athlon 64 and AMD Opteron processors run any 32-bit legacy O/S
Compatible all legacy Drivers, OS & BIOS
No application recompile required, no emulation layer
64-bit OS
Desired applications can be written/ported to leverage the full 64-bit capabilities of x86-64
Migrate only where warranted, and at the user’s pace
All 32-bit applications run under 64-bit OS
BIOS is standard x86 32-bit code.
Transfer to 64-bit operation occurs under OS load/startup control
64-bit mode does not use segmentation - Flat addressing
The right way to get to 64 bits:
Investment Protection, Flexibility, No Penalty to 32 bit Performance
April 16, 2017
Computation Products Group

38. The Next Generation Processor

39. AMD Opteron™ & AMD Athlon™ 64
Background
Quick overview of chip configurations
Core improvements over AMD’s 7th Generation Athlon Processors
Integrated Memory Controller
Multi-processor performance
HyperTransport Technology
April 16, 2017
Computation Products Group

40. AMD 64-bit Family of Processors
4P - 8P HPC
Cluster
800 Series
(up to 8 way)
2P Servers
Workstation
Performance
200 Series
(2 way)
1P Server
& Workstation
100 Series
(1 way)
1P Desktop
& Mobile
Price
April 16, 2017
Computation Products Group

41. True Customer-Centric Innovation
Performance-enhancing features include:
Performance
High-bandwidth integrated memory controller scales with processor frequency and number of processors
DDR Memory
Controller L2
Cache
L1 Instruction L1
Data
AMD64
Processor Core
Compatibility
Approximately 10,000 legacy applications at time of launch
Scalability
Reduced costs for high-end systems
Removes I/O bottlenecks
Easy multiprocessor scaling
HyperTransport™
. . .
April 16, 2017
Computation Products Group

42. AMD Athlon™ 64 Processor AMD64: Desktop Processor L2 Cache
8 Byte memory controller supporting 200, 266, & 333 MHz DDR Memory
CHIPKILL ECC with x4 DRAMs
Drive up to 4 registered DIMMs
4 DIMMs <266MHz
2 DIMMs >333MHz
Future memory technology supported as it is defined
Up to 4GB x4 DRAMS (4GB DIMMs)
HyperTransport™ Technology I/O
On chip L1 & L2 cache
64KB L1 ICache, 64KB L1 DCache
Up to 1M ECC protected L2 Cache
740-pin µPGA Package
DDR Memory
Controller 72 L2
Cache
L1 Instruction L1
Data
AMD64
Processor Core
HyperTransport™ 16
Replaces Address, Data and Control Bus
April 16, 2017
Computation Products Group

43. 1P AMD Athlon™ 64 Desktop Processor System
System Strengths
Memory Latency, Bandwidth and memory reach:
240 physical ( 1 Terabyte)
248 virtual
I/O Latency and Bandwidth ~1600M T/sec
6.4 GB/s
64-bit CPU
More Reliable
Lower Chip count
Improved machine check
Improved error handling
4GB DRAM
AMD Athlon™ 64
MHz
72-Bit Reg DDR
16x MTs
533Mhz
AMD-8151™
AGP 8X
AGP 8X
AMD-8111TM
I/O Hub
PCI 33/32
EIDE
FLASH
LPC
SIO
USB1.1,2.0
AC97
ACR 1.0
MII
10/100
NIC
April 16, 2017
Computation Products Group

44. 1P AMD Opteron™ 100 Series AMD64: 1 way Value Server L2 Cache
16 Byte memory controller supporting 200, 266, & 333 MHz DDR Memory
CHIPKILL ECC with x4 DRAMs
Drive up to 8 registered DIMMs
8 DIMMs <266MHz
4 DIMMs >333MHz
Future memory technology supported as it is defined
Up to 4GB x4 DRAMS (4GB DIMMs)
Three 16-bit non-Coherent HyperTransport™ Technology Links
On chip L1 & L2 cache
64KB L1 ICache, 64KB L1 DCache
Up to 1M ECC protected L2 Cache
940-pin µPGA Package
18 CAS lines for 32GB of memory
72/144
DDR Memory
Controller L2
Cache
L1 Instruction L1
Data
AMD64
Processor Core
HyperTransport™ 16 16 16
Replaces Address, Data and Control Bus
April 16, 2017
Computation Products Group

45. 1P AMD Opteron™ 100 Desktop Processor System
PCI-X
PCI-X
AMD-8131™
PCI-X Tunnel
PCI-X
8GB DRAM
AMD Opteron™
System Strengths
Ideal for cost sensitive designs system where I/O is the critical commodity
Storage servers
Low end DCC workstations
AMD-8131™
PCI-X Tunnel
16x MTs
PCI-X
AMD-8151™
AGP 8X
533Mhz
AGP 8X
AMD-8111TM
I/O Hub
PCI 33/32
FLASH
LPC
EIDE
SIO
USB1.1,2.0
AC97
ACR 1.0
MII
10/100
NIC
April 16, 2017
Computation Products Group

46. 2P - AMD Opteron™ 200 Series AMD64: 2 Way Performance Server L2 Cache
16 Byte memory controller supporting 200, 266, & 333 MHz DDR Memory
CHIPKILL ECC with x4 DRAMs
Drive up to 8 registered DIMMs
8 DIMMs <266MHz
4 DIMMs >333MHz
Future memory technology supported as it is defined
Up to 4GB x4 DRAMS (4GB DIMMs)
One coherent and two 16-bit non-Coherent HyperTransport™ Technology Links
On chip L1 & L2 cache
64KB L1 ICache, 64KB L1 DCache
Up to 1M ECC protected L2 Cache
940-pin µPGA Package
18 CAS lines for 32GB of memory
72/144
DDR Memory
Controller L2
Cache
L1 Instruction L1
Data
AMD64
Processor Core
HyperTransport™ 16 16 16
Replaces Address, Data and Control Bus
April 16, 2017
Computation Products Group

47. 2P AMD Opteron™ 200 Server System Strengths
PCI-X
PCI-X
PCI-X
PCI-X
AMD-8131™
PCI-X Tunnel
AMD-8131™
PCI-X Tunnel
8GB DRAM
8GB DRAM
AMD Opteron™
AMD Opteron™
PCI-X
PCI-X
Bridge or SSL/IPSec.
AMD-8131™
PCI-X Tunnel
System Strengths
Ideal for systems where large flat memory is important (16GB of SMP memory)
Data mining
Rational Data Base applications
AMD-8111TM
I/O Hub
PCI 33/32
EIDE
FLASH
LPC
SIO
USB1.1,2.0
AC97
ACR 1.0
MII
10/100
NIC
April 16, 2017
Computation Products Group

48. 4P - 8P AMD Opteron™ 800 AMD64: 4 - 8 Way Performance Server L2 Cache
16 Byte memory controller supporting 200, 266, & 333 MHz DDR Memory
CHIPKILL ECC with x4 DRAMs
Drive up to 8 registered DIMMs
8 DIMMs <266MHz
4 DIMMs >333MHz
Future memory technology supported as it is defined
Up to 4GB x4 DRAMS (4GB DIMMs)
Three 16-bit Coherent HyperTransport™ Technology Links
On chip L1 & L2 cache
64KB L1 ICache, 64KB L1 DCache
Up to 1M ECC protected L2 Cache
940-pin µPGA Package
72/144
DDR Memory
Controller L2
Cache
L1 Instruction L1
Data
AMD64
Processor Core
HyperTransport™ 16 16 16
April 16, 2017
Computation Products Group

49. AMD Opteron™ 800 HPC Processing Node
HPC Strengths
Flat SMP like Memory Model:
All four reside with the same 248 memory map
Expandable to 8P NUMA
Glue-less Coherent multi-processing:
low Latency and high Bandwidth ~1600M T/sec (6.4 GB/s)
32GB of High B/W external memory bus (>5.3GB/sec.)
Native high B/W memory map I/O (>25Gbits/sec.)
April 16, 2017
Computation Products Group

50. AMD Opteron™ Processor Model _ _ _
Model Number Implementation
Model Number Implementation
First digit = scalability of AMD Opteron processor
Second and third digits = relative performance among AMD Opteron processors
Model number conveys directional improvement
AMD Opteron™ Processor Model _ _ _
Clock
Clock
Model
Model
AMD Opteron™
800 Series
1.4GHz
1.4GHz
840
840
1.6GHz
1.6GHz
842
842
Up to 8 way
1.8GHz
1.8GHz
844
844
2.0GHz
2.0GHz
846
846
AMD Opteron™
Clock
Clock
Model
Model
200 Series
1.4GHz
1.4GHz
240
240
Up to 2 way
1.6GHz
1.6GHz
242
242
1.8GHz
1.8GHz
244
244
2.0GHz
2.0GHz
246
246
AMD Opteron™
Clock
Clock
Model
Model
100 Series
1.8GHz
2.0GHz
144
146
1 way
2.0GHz
146

51. Price Performance Positioning
800
200
A solution unto it self
Performance
100 1M
256K
Price
April 16, 2017
Computation Products Group

52. Opteron™ Processor Architecture

53. Instruction Control Unit (72 entries)
The Elements of the CPU L2
Cache L1
Instruction Cache
64KB
Fetch
Branch
Prediction
Scan/Align
Fastpath
Microcode Engine L1
Data Cache
64KB
mOPs
Bus Unit
Instruction Control Unit (72 entries)
System
Request
Queue
Int Decode & Rename
FP Decode & Rename
Crossbar
44-entry
Load/Store
Queue
Res
Res
Res
36-entry FP scheduler
Memory
Controller
AGU
AGU
AGU
FADD
FMUL
FMISC
ALU
ALU
ALU
HyperTransportTM
MULT
April 16, 2017
Computation Products Group

54. Processor Throughput
Supply 16 instruction bytes to the decoder per cycle
Convert x86 instructions to fixed length µOPs
24-entry integer scheduler can Dispatch 3 µOPs per cycle to integer/FP schedulers
Instructions use one of two decoding pipelines
Fastpath: instructions which are decoded in to two or fewer mOPs are decoded by hardware and then packed into 3 dispatch positions
Microcode: x86 instructions which are decoded in to more than two mOPs, calculate microcode ROM entry point and fetch sequence from Microcode ROM
Point out where the 2 to 3% of die size is for x86 (decode and pack logic)
Compared to AMD Athlon™ XP, more instructions use the Fastpath
Eg: Packed SSE is microcoded in AMD Athlon XP and Fastpath in AMD Opteron  processors
AMD Opteron has 8% fewer microcoded instructions for SPECint2000
AMD Opteron has 28% fewer microcoded instructions for SPECfp2000
April 16, 2017
Computation Products Group

55. Floating Point & Integer Performance
FPU Throughput
SSE2, x87
Theoretical: (1 Mul + 1 Add)/cycle
Realized: 1.9 FLOPs/cycle
SSE, 3DNow!
Theoretical: (2 Mul + 2 Add)/cycle
Realized: 3.4+ FLOPs/cycle
32-bit Integer Throughput
1 add / clock cycle
1 multiply / clock cycle
Multiply latency has shrunk from 5 cycles on AMD AthlonTM to 3 cycles on the AMD Opteron™
64-bit Integer Throughput
1 multiply every other clock cycle
Multiply latency is 4 cycles
Integer Instruction Scheduler
Out Of Order (OOO) from a queue of 24* Integer Macro-Ops
*AthlonTM Instruction Scheduler is 18 Macro-Ops deep
April 16, 2017
Computation Products Group

56. Internal Caching L2 Cache Bus Unit L1 Instruction Cache 64KB L1
L1 caches
64k bytes instruction and data
2-way set associative
Data Cache is ECC protected
Instruction Cache is Parity protected
L2 cache
Caches instruction and data streams
16-way set associative, ECC protected
>2X Athlon XP L2  L1 bandwidth
Improved Translation Look-aside Buffer for large multiprocessor workloads
Twice the size and Lower latencies then AMD Athlon XP
L2 Translation Look-aside Buffer
512 entry - 4-way associative
L1 Translation Look-aside Buffer
32 entry Instruction & Data -fully associative
Machine check architecture for reporting failures L2
Cache L1
Instruction Cache
64KB L1
Data Cache
64KB
Bus Unit
The TLB flush filter is a structure used to track processor and external
writes to all the pages that make up the translations currently stored in
the on-chip TLBs. When a MOV to CR3 is executed (which normally causes the
TLBs to be flushed), the state of the flush filter is examined by the CPU.
If the on-chip TLBs are still coherent with external memory, then the flush
is not performed (resulting in a performance improvement when swapping
between different processes with different page tables).
Yes, there are four TLBs (IC-L1, IC-L2, DC-L1, DC-L2), all are parity
protected. Failures are detected only when someone tries to use an entry
with a parity error (ie. no scrubbers).
Failures in either of the IC tlb arrays are recoverable, we flush the TLB
and restart the access. Failures in either of the DC tlb arrays are fatal,
we take a fatal machine check error.
44-entry
Load/Store
Queue
April 16, 2017
Computation Products Group

57. Reliability Features L1 Cache L2 cache
Data cache is ECC protected via background scrubber
Instruction cache is parity protected upon R/W
L2 cache
Cache Tag arrays are ECC protected via background scrubber
Instructions are parity protected, Data is ECC protected
ECC bit reused for Branch Prediction and Instruction Decode (end bits)
DRAM is ECC protected with chipkill ECC support
Each fetch is parity checked
ECC via scrubber – period is user programmable for 40ns to 84usec.
Remaining arrays are parity protected
Instruction cache, tags and TLBs
Data tags and TLBs
Generally read only data which can be recovered
Machine Check Architecture
Report failures and predictive failure results
ECC
Branch Predictor
ThermTrip
Memory scrubbers
April 16, 2017
Computation Products Group

58. Branch Prediction Improvements
Fetch
Branch
Prediction
Full L1 Cache Coverage
Twice the selectors as AMD Athlon™ XP
4K Branch Target Addresses
Backed up by Branch Address Calculator
4 cycle correction for unconditional relative branches
16K Bimodal Counters
Four times AMD Athlon XP
Full Pre-decode and Branch Identification in L2 Cache
New and unique to AMD Opteron Family of Processors
Reuses L2 ECC bits on clean/shared instruction lines and on extra bit
Scan/Align
Fastpath
Microcode Engine
mOPs
Instruction Control Unit (72 entries)
April 16, 2017
Computation Products Group

59. Integrated Northbridge

60. Firmware View of Northbridge
Performs same functions found in Northbridge
Memory Controller – fully integrated
Host-Bridge function as defined by the PCI spec
PCI to PCI Bridge as defined by the PCI spec
Graphics Address Resolution Table (GART)
Multi-processor coherency
Controlled via PCI configuration registers
Memory controller configuration
HyperTransport™ technology routing
Configured by Firmware
HyperTransport™ initialization via Hardware
Auto-size, coherent or non-coherent, “Legacy” path to the ROM in Southbridge
HyperTransport™ technology speed and routing via firmware
Everything else in firmware follows existing paradigms
PCI enumeration
Memory sizing and configuration
I/O controller setup
System
Request
Queue
Crossbar
Memory
Controller
HyperTransportTM
April 16, 2017
Computation Products Group

61. Systems View of Northbridge
(Assumes a 2GHz processor Clock)
April 16, 2017
Computation Products Group

62. HyperTransport™ Technology
Screaming I/O for chip-to-chip communication
High bandwidth
Point-to-point links
Split transaction and full duplex
Differential Signaling
Tunneling capability
HyperTransport Links
Three 16-bit links (3.2 GB/s per direction)
Reduced pin count compared to the typical Bus based systems
Compatible with high-volume PC board infrastructure
Each can be:
cHT: coherent (Processor-to-Processor) link or,
ncHT: non-coherent (Processor-to-I/O) link
For more info see:
Enables scalable 2-8 processor Cache-Coherent MP systems
Glueless MP
April 16, 2017
Computation Products Group

63. Performance

64. Multi-Processor Performance Evaluation Simulation Parameters
Microbenchmark Simulations:
RTL based
Cycle accurate
DRAM Page hit
System Parameters:
AMD Opteron 2 GHz CPU
Memory Clock = 333 MHz Data Rate
Registered PC2700 DDR memory
DRAM width = 128 bits interleaved
CAS latency = 2.5 memory clocks
HT frequency = 1600 MHz Data Rate (16 bits)
DDR Peak Bandwidth = 5.4 GB/s
HT Peak Bandwidth = 3.2 GB/s (each direction)
April 16, 2017
Computation Products Group

65. AMD Opteron™ processor estimates
SPECint® Performance
SPECint 2000
*Based on 2GHz lab hardware
Using 32 bit binaries
1300
1200
1100
AMD Opteron™ processor estimates
1000
900
SPECint 2000
800
Intel Xeon processor*
700
600
500
400
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
Operating Frequency [MHz]
*Source
April 16, 2017
Computation Products Group

66. SPECfp® Performance Comparison
*Based on 2GHz lab hardware
Using 32 bit binaries
SPECfp 2000
AMD Opteron™ processor estimates
1500 B
1400 B
1300 A A
1200 A
1100
1000
900
Intel Xeon™ processor*
800
What were the x86 WS market volumes in the 1Q02 of 2002 by CPU Type? This slide says it all about the current landscape of the x86 market in 1Q02. There are two parts to the slide.
Top Section of the Slide:
This chart was created internally from the Gartner COGNOS Workstation 1Q02 Data cube. What it illustrates is the workstation market by volume price bands and market share percentages associated with those volumes. The first column in red shows the P4 volumes by price bands and the second column in blue shows Xeon volumes. These numbers are in systems, NOT PROCESSORS. This chart shows how 1P P4’s are dominating the value, volume and performance segments of the market. P4 in 1Q02 account for 66% of the volume. Xeon 2P accounts for 34%.
Bottom Section of the Slide:
This part of the slide is a historical look back at the workstation market from a 1P vs. 2P configured platform perspective from 1Q00 – 1Q02. What this shows is the “inflection” point in the 2Q01 where the volume of 1P platforms overtook the volumes of the 2P based platforms. There are three reasons that analysts give for this transition.
First, when the P4 was introduced in Nov of 2000, this was the beginning of the P3 phase out. Over the next two quarters, P4 entered the channel and began to sell, however, the problem was that there is NO 2P chipset for the P4 in the value and volume space like there was with P3.
Secondly, in order to get a 2P based platform, end-users were forced to buy P4 Xeon. Given the additional cost of RDRAM and the price premiums on XEON, most were not willing to spend the additional money.
Third is Intel’s push the adoption of HyperThreading in the market. This story plays well into the P4 1P processor platform strategy. Recent news articles indicated the we will see HyperThreading in the desktop by 2003.
This is a great “Sell Up” proposition from Intel.
Volumes in these slides are by platforms, NOT PROCESSORS.
~400 MHz
~ 1100 MHz
700
600
500 A B A B
400
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
5000
Operating Frequency [MHz]
*Sourcehttp://
April 16, 2017
Computation Products Group

67. SPECfp 2000 Base Competitive Summary (32-bit Windows, PC2700 CAS2.5)
SPECfp® 2000 Scores
1400
AMD Opteron
1200
1000
AMD Opteron
800
P4 533FSB
Score
600
P4 400FSB
Redesign effort
400
200
PIII 133FSB
0.5 1
1.5 2
2.5 3
CPU Frequency (GHz)
Base (IA32)
Peak(IA32)
AMD Opteron Processor (Estimated Performance)
Source:
April 16, 2017
Computation Products Group

68. AMD Opteron SPEC projections compared to Alpha EV7
AMD Opteron should be more cost-effective versus Alpha EV7
Standards versus Proprietary
Millions per month versus 100’s
April 16, 2017
Computation Products Group

69. AMD Opteron SPEC projections compared to Itanium-2
AMD Opteron will be more cost-effective than Itanium-2
Standards versus Proprietary
Millions per month versus 1,000’s
April 16, 2017
Computation Products Group

70. Integrated Memory Controller Latency (Local Memory Access, Registered Memory, CAS 2.5)
1.6GHz
PC2700
85-95ns
(L1 cache miss,TLB miss)
Stride
(bytes)
Time (ns)
Stride >1M
65ns
(L1 cache miss,TLB hit)
Why no false collision?
32k< Stride <1M
Stride <32k
Block Size (bytes)
April 16, 2017
Computation Products Group

71. Integrated Memory Controller Performance
Peak Bandwidth
1.6GHz AMD Opteron™ 800 Latency (333MHz PC2700 DIM)
Page Hit (0 hop) ~ 65nS Page Miss (0 hop) ~95nS
Page Hit (1 hop) ~ 100nS Page Miss (1 hop) ~120nS
Page Hit (2 hop) ~ 140nS Page Miss (2 hop) ~160nS
Note: AMD Athlon™ and competitive 1P processors - Page Hit (0 hop) ~ 170nS
Peak Memory Bandwidth
64-Bit DCT
128-Bit DCT
 DDR200 PC1600
1.6GB/s
3.2GB/s
 DDR266 PC2100
2.1GB/s
4.2GB/s
 DDR333 PC2700
2.7GB/s
5.33GB/s
Here is the peak bandwidth and latency.
PC2700 memory on 16byte bus provides 5.33GB/s peak bandwidth.
These latencies are for an idle system, one read launched, page miss
0-Hop DP buries the probe response latencies
0-Hop 4P is where you start to see the probe latency exceed the DRAM access
1,2,3 hops, the probe latencies are buried
April 16, 2017
Computation Products Group

72. Symmetric Multi Processing (SMP)
Advantages
The whole system appears like a single-processor system
The OS does not need to know how memory is laid out
The programmer need not worry about memory location
Disadvantages
Systems are not scalable:The systems bus becomes a HUGE bottleneck as more processors are added.
Hardware mechanisms are costly as they are specially built for low volume systems (e.g. the number of 8 ways is less than 10% that of 2 way systems)
With a large number of cache misses, the bus transfer activity rises and the whole system gets slower. OS
System Memory
Task1/thread3
Task2/thread6
Task3/thread5
Integrity of data
The most critical steps when running the same application on different CPU's, are those parts of the source code, where shared data is modified. The system kernel has to make sure, that only one process per time is allowed to write. So all other processes have to stop and wait until the first process has finished writing. This problem is solved through locks. A lock is a bit within memory, used by processes to regulate access to critical steps of the source code.
If a process wants to enter a critical step, he checks the lock first. Is the bit zero, the process sets it to one and enters the critical code.
If the bit is one, the process checks the bit until it is zero again (spin lock). The process keeps its CPU meanwhile.
Waiting means lower performance. So locks have to be sized. The smaller the critical step is, the more likely it is accessible.
Task4/thread1
Task5/thread4
Intra-node Communication
Task6/thread2
April 16, 2017
Computation Products Group

73. Non Uniform Memory Architectures (NUMA)
Advantages
NUMA architectures are the next logical step in scaling from SMP architectures.
They bring dramatic scalability advantages
Task1/thread1
Task2/thread2
Task3/thread3
Task4/thread4
Task5/thread5
Task6/thread6 OS
Task7/thread7
Task8/thread8
Task9/thread9
Task10/thread10
Task11/thread11
Task12/thread12
Disadvantages
May require specialized HW to implement
OS needs to be more aware of memory lay out
The programmer may need to be aware of memory layout for optimum performance
CACHE Coherency protocols are more complex.
Non-Uniform Memory Access or NUMA is a computer memory architecture, used in multiprocessors, where the memory access time depends on the memory location. A processor can access its own local memory faster than non-local memory (memory which is local to another processor or shared between processors).
April 16, 2017
Computation Products Group

74. Sufficiently Uniform Memory Organization (SUMO)
Advantages
Software view of memory is SMP
Latency difference between local & remote memory is a function of the number of processors in the node
1P and 2P look like a SMP machine
3P and 4P are NUMA like but can still be viewed as a ccUMA or asymmetric SMP node
>4P can be viewed as ccUMA and depending on CACHE hit rate, may or may not required NUMA aware OS
Physical address space is flat and can be viewed as fully coherent or not (MOEIS state)
DRAM can be contiguous or interleaved
Additional processor nodes bring true increased memory bandwidth
Designed for lower overall system chip count (glue-less interface)
Disadvantages
3P and 4P nodes work better if the OS is “aware” of the memory map
>4P may require a NUMA aware OS if the CACHE hit rate is low
April 16, 2017
Computation Products Group

75. Future NUMA Systems Scaling beyond 8 Processor
Interconnect Fabric 4P
SW0
SW1 4P
SW2
SW3 4P
SW2
SW3 4P
SW2
SW3
Scaling beyond 8P is enabled
External Coherent HyperTransport switch Coherent Interconnect
Snoop filter
Data caching
Up to 16 processors within the same 240 SPM memory space
April 16, 2017
Computation Products Group

76. AMD Opteron Support ICs

77. AMD Opteron™ Support IC’s
AMD is committed to deliver the highest quality systems solutions
Providing a family of x64-64 processors is just the start
AMD will promote and enable a broad range of HyperTransport™ support silicon from internal and external design efforts.
AMD, with the HyperTransport™ consortium, will grow the HyperTransport™ eco-system
April 16, 2017
Computation Products Group

78. HyperTransport Technology Consortium
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Computation Products Group

79. AMD-8131™ HyperTransport™ PCI-X Tunnel
Dual PCIx Master
Each PCI-X Bridge independently supports
66, 100, 133MHz PCI-X Protocol
33 and 66MHz PCI 2.2 Protocol
SHPC Controller
64-bit data path
IOAPIC
Arbiter for up to 5 masters
Hot-swap
HyperTransportTM Support: 16/16 up, 8/8 down, independent support for
Up to 1600MT/s up and down
Full Link Auto sizing and speed selection
829 OBGA, 37.5mm body, 1.27mm pitch, full array, 6-Layer Motherboard Breakout
AMD Opteron Or
AMD Athlon™64
16x MTs
AMD-8131
HyperTransport™ Dual PCI-X
8x8 800MTs
AMD-8111TM
I/O Hub
33Mhz
FLASH
LPC
SIO
USB1.0,2.0
AC97
UDMA100
10/100 Ethernet
100 BaseT
10/100 Phy
April 16, 2017
Computation Products Group

80. AMD-8111™ HyperTransport™ I/O Hub
Engineered from past successful AMD I/O hub development efforts
8x8 wide 200 MHz DDR HyperTransport™ technology interface (800MB/s aggregate BW)
Enhanced 10/100 Ethernet MAC
USB1.1, USB2.0, EDMA, AC’97
LPC for BIOS ROM and Super I/O
PCI version /32 Bridge (“legacy”)
Supports arbitration of up to 8 external masters
SMbus 1.0 and 2.0 controllers
492 PBGA, 35x35mm body, 1.27mm pitch
8x8 HyperTransportTM @ 800MHz
33Mhz
AMD-8111TM
I/O Hub
EIDE
FLASH
LPC
USB1.1,2.0
AC97
MII
SIO
NIC
10/100 BaseT
April 16, 2017
Computation Products Group

81. AMD-8151™ HyperTransport™ AGP Tunnel
8xAGP
Fully AGP 3.0 Compliant
66,133,266,533MHz operation
HyperTransportTM Support: 16/ up, 8/8 down, independent support for
Up to 1600MT/s up, Up to 800MT/s down
Full Link Auto sizing and speed selection
564 OBGA, 31x31mm body, mm pitch, full array
AMD Opteron™ Or
AMD Athlon™64
8x AGP
AMD 8151
HyperTransport™
AGP
Int Gfx
8x8 800MTs
33Mhz
AMD-8111TM
I/O Hub
FLASH
LPC
SIO
USB1.0,2.0
AC97
UDMA100
10/100 Ethernet
100 BaseT
10/100 Phy
April 16, 2017
Computation Products Group

82. Opteron™ & Athlon™ Server Chipset Roadmap
HyperTransport
Second Generation
PCI Device
AMD-8131
HyperTransport
PCI-X Tunnel
2 PCI-X Bridges
AMD-8151
HyperTransport
AGP Tunnel
8th Generation
AMD-8111
HyperTransport
I/O Hub
Second Generation HyperTransport™
I/O Hub
AMD-760MP/MPX
7th Generation
2005
2H02
2003
2004
April 16, 2017
Computation Products Group

83. Desktop Infrastructure Roadmap Athlon 64 Desktop Chipset Roadmap
April 16, 2017
Computation Products Group

84. A Growing ecosystem of HyperTransport™ enabled ICs
Available today:
Dual MIPS processor - Broadcom BCM1250
PCI 66/64 Bridge from Alliance Semi.
NITROX Security Macro Processor from Cavium Networks
FPGA from XILINX and Altera
Announced:
RM9000 MIPS processor from PMC Sierra
4 Port 8/8 HyperTransportTM switch swap support from Alliance Semi.
SSL/TLS Record Processing Systems – Broadcom BC5850
Luminance™ Modular Array Technology - Lightspeed Semiconductor
Planned:
InfiniBand™ Bridge
Proprietary High Speed Interconnect
4 Port 16/16 non-coherent switch
4 port 16/16 coherent switch
PCI-X Bridges
April 16, 2017
Computation Products Group

85. HyperTransportTM technology 4-way 16/16 Non-Coherent Switch
Extends the fabric by re-mapping Unit_IDs at each port
Tracks path of packet that pass through it, guaranteeing the same return path
Records the incoming Unit_ID so it can be restored in the response packet
Follows same rules as Processor Host interface
Peer-to-peer through the switch freeing up the host
Facilitates multiple Host fabrics
April 16, 2017
Computation Products Group

86. Nine channel GigE Firewall
AMD Opteron™
8x8 HyperTransport™
1000M transfers/sec.
16x MT/s
133Mhz
AMD-8131TM
PCIX Tunnel
133Mhz
PCI-X
PCI-X
8x8 400MT/s
VGA
PCI
Graphics
AMD-8111TM
I/O Hub
Legacy PCI
FLASH
LPC
SIO
Zircon BMC
USB1.0
AC97
UDMA133
MII
100 BaseT
Management LAN
10/100 Phy
April 16, 2017
Computation Products Group

87. AMD Opteron DP - 2P Server with SSL/IPsec encryption
Security Macro Processor
RM9000x2
DDR SDRAM
SysAD Bus
SP 8/8
Switch
SP1011
PCI Bridge
PCI 66/64
April 16, 2017
Computation Products Group

88. 1U/1P AMD Opteron™ Server
April 16, 2017
Computation Products Group

89. 1U/2P AMD Opteron™ Server
April 16, 2017
Computation Products Group

90. 4P Coherent System Based on two 2P MP Nodes
8-G DRAM
MHz
9 byte Reg. DDR
MHz
9 byte Reg. DDR
AMD Opteron DP
AMD Opteron DP
Probe directory
Horis
SRAM
MHz
9 byte Reg. DDR
MHz
9 byte Reg. DDR
8-G DRAM
AMD Opteron DP
AMD Opteron DP
Legacy PCI
16x MT/s
VGA
PCI
Graphics
AMD-8111TM
I/O Hub
PCI-X
AMD-8131TM
PCI-X Tunnel
PCI-X
FLASH
LPC
SIO
Management
100 BaseT
Management LAN
USB1.0
AC97
UDMA133
MII
10/100 Phy
April 16, 2017
Computation Products Group

91. AMD Opteron™ Beowulf 4P SMP Processing Node
To AMD 8131 Tunnel
To AMD 8131 Tunnel
AMD Opteron™
MHz
9 byte Reg. DDR
8GB DRAM
AMD Opteron
8-G DRAM
MHz
9 byte Reg. DDR
One 4P SMP node
16G-flops
32GB DRAM
10GB/sec. Memory BW
AMD Opteron
8GB DRAM
MHz
9 byte Reg. DDR
AMD Opteron
16x MT/s
VGA
PCI
Graphics
AMD-8111TM
I/O Hub
Legacy PCI
PCI-X
AMD-8131TM
PCI-X Tunnel
PCI-X
FLASH
LPC
SIO
Management
100 BaseT
Management LAN
USB1.0
AC97
UDMA133
MII
10/100 Phy
April 16, 2017
Computation Products Group

92. HyperTransport Technology on the Backplane – non coherent interconnect
SI4041
Switch
4P Blade
Switches and 8111 on the backplane
Hot swap connection
April 16, 2017
Computation Products Group

93. Two - 8 Processor System Topologies (NUMA)
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Computation Products Group

94. 2P Server with Add-on Accelerator Daughter Card
PCI-X
PCI-X
PCI-X
PCI-X
AMD-8131™
PCI-X Tunnel
AMD-8131
PCI-X Tunnel
8GB DRAM
AMD Opteron™
AMD Opteron
MHz
72-Bit Reg DDR
PCI-X
PCI-X
AMD-8131
PCI-X Tunnel
PCI 33/32
Luminance™
Modular
Array ASIC
Interface Device
8x8 1.6GB/sec.
AMD-8111TM
I/O Hub
EIDE
FLASH
HyperTransport-enabled
daughter card
LPC
USB1.1,2.0
AC97
ACR 1.0
GMII
SIO
10/100
NIC
April 16, 2017
Computation Products Group

95. AMD Athlon 64 1P Blade Design
4GB DRAM
AMD Athlon 64™
Ultra low cost Blade design
4GB 333MHz DRAM
2GHz processor
~35 Watts
Luminance Device
Boots the Processor
Provides HCA network interface
16x16 1,000MT/s
Boot ROM
Luminance™
Modular
Array ASIC
Interface Device
HCA Interface
April 16, 2017
Computation Products Group

96. AMD Opteron™ Processor DP – 2P Graphics WorkstationTM
April 16, 2017
Computation Products Group

97. 2P AMD Opteron™ Processor Graphics Workstation (Cave)
April 16, 2017
Computation Products Group

98. High density SprayCooled Blade Configuration
4P – 16G-flop Blade Design
64GB of SMP DRAM
ASIC boots the 4P unit
PCI-X provides all I/O
Vapor cooled in sealed enclosure
External VRM
April 16, 2017
Computation Products Group

99. How ISR SprayCoolTM Technology Works
b. Vapor travels though the heat exchanger to be condensed
a. As the electronics are sprayed, the fluid vaporizes, cooling the electronics to a low, stable temperature.
c. Fluid collects in reservoir
d. Fluid is purified by the filtration system
f. Sealed enclosure protects electronics from dust, dirt, salt-air…
e. Fluid is pumped back into the electronics in a continuous cycle
April 16, 2017
Computation Products Group

100. High Density HPC Cluster SprayCool Technology from ISR
16 cards
16G-flops/card
256G-flops peak throughput
64GB of memory per card
1TerraByte of sys. Memory
240 cubic inches
114M-flops/cubic inch
4.27GB of memory storage cubic inch
~6K watts
~3 watts/cubic inch
16”
10”
14”
April 16, 2017
Computation Products Group

101. AMD Reference Design Kits

102. Four Hardware platforms
Solo (AMD): 1P AMD Opteron mother-board for Desk top applications
Serenade (AMD): 2P AMD Opteron system board for HPC and server applications
Quartet (AMD): 4U-4P AMD Opteron system board for HPC and server applications
Khperi (Newisys): 1U-2P AMD Opteron server board
April 16, 2017
Computation Products Group

103. Solo Features Athlon64 Uni-processor
Two Unbuffered PC2700, PC2100 DDR DIMMs
AMD 8151 AGP8X – HyperTransport Tunnel
AMD 8111 I/O Hub
Four PCI 32b 33MHz slots
Two ATA-100 EIDE connectors
Size USB 2.0 ports
3 on back panel, 2 on front panel, and 1 on ACR
AC ’97 audio
SMBus 1.0 and 2.0 support
One ACR slot; 1 Fan with sense and 1 Fan without sense
Floppy, serial, parallel, 2 PS/2 and 2 IEEE 1394a connectors
LPC Super I/O with 2 fans with sense
4-layer ATX form factor with ATX power supply
PC2001, WHQL, Energy Star, WFM 2.0 compliant
April 16, 2017
Computation Products Group

104. Hammer Performance Desktop (Solo-RDK)
April 16, 2017
Computation Products Group

105. 1U/2P “Serenade” CPU/Memory Complex I/O Management Storage Physicals
Opteron processor 200 Series (supports up to 2 processors)
Four banks of 128bit registered DDR memory/CPU (DDR )
I/O
Full size PCI-X slots: Two PCI-X 64/100 MHz or one PCI-X 64/133 (none hot plug-able)
One mini-PCI slot
Dual Broadcom 10/100/1000 Ethernet onboard
Dual LSI U320 SCSI (one channel to disk, one channel to rear expansion)
Single USB1.1: to front
SIO (Floppy, Serial, Keyboard, Mouse)
Management
Single dedicated management, LAN10/100
Optional BMC management controller, IPMI 1.5 compliant
Storage
Dual drive bays: (standard) IDE or (standard or hot-swap) SCSI drives
Slim-line IDE CD-ROM or slim-line floppy drive
Physicals
1U Rack-mount server form factor, tool-less access, full extension slide rails
Single 500W power-supply, rear accessible to line cord
Removable blowers, cooling performed front-to-rear (passive CPU heatsinks)
Front LED panel with activity and status: PWR, RESET, USB , PCI-Video
Dimensions: (1U) x 19” W x 28” D
April 16, 2017
Computation Products Group

106. 1U/2P “Serenade” Front View
28”
500W
Power Supply
CDROM or Floppy (slimline)
Drive Carriers (x2)
(SCSI hot swappable)
10 Redundant Blowers
(front to back cooling)
AMD Opteron 200 Series
(x2)
32/33MHz PCI
(half-height/half length)
(Video option)
8 DIMMs DDR ECC (4DIMMs/CPU)
SCSI Disk Option
(Mini-PCI)
Full Size PCI-X Slots (x2) 64/100 MHz
or single PCI-X 64/133
(riser w/sideband)
April 16, 2017
Computation Products Group

107. 1U/2P “Serenade” Rear View
Full Size PCI-X Slots (x2) 64/100 MHz
or single PCI-X 64/133
module assembly
(riser w/sideband)
AMD Opteron 200 Series (x2)
cooling ducts
Dedicated 10/100 IPMI Management Port
Dual 10/100/1000 ENET
32/33MHz PCI
(half-height/half length)
(std. half-height video option)
PS2 ports
U320 SCSI Option
(Mini-PCI)
USB port
April 16, 2017
Computation Products Group

108. “Quartet”: 4U/4P SledgeHammer MP 940-pin Processor
April 16, 2017
Computation Products Group

109. Quartet System Features
4U Rack-mount server form factor (25” deep) EIA-Std
4P Opteron (940-pin)
Four banks of 128bit registered DDR memory per CPU (designed for DDR-333) – 16 Total
Five full size PCI-X slots (AMD 8131):
Two PCI-X 64/133 MHz (hot plug-able)
Three PCI-X 64/66 MHz
Ethernet Ports:
Dual Broadcom 10/100/1000 Ethernet onboard
Single 10/100 (AMD-8111)
Dual LSI U320 SCSI (one channel to disk, one channel to rear expansion)
System Management: Qlogic UL BMC IPMI 1.5 via dedicated LAN/Modem
April 16, 2017
Computation Products Group

110. Quartet System Features (cont)
Dual IDE: Slim-line CD-ROM, Slim Floppy
Dual USB: one front, one rear
SIO (Floppy, Serial, Keyboard, Mouse)
Storage: Four 1” hot-swap Ultra320 SCSI drives
Video: ATI 4 Meg (via card option PCI 32/33)
Three 500W hot-swap power-supplies (2+1 redundancy) for 4U; rear accessible to three line cords
Hot-swap redundant fans (10)
Front LED panel with activity and status: PWR, RESET, USB , PCI-Video
Full extension slide rails
Dimensions: 5.25” H x 19” W x 28” D (*5.25” is main/processor section; an additional 1.75” is the power supply bay)
Cooling front to rear (passive CPU heatsinks)
Tool-less access
April 16, 2017
Computation Products Group

111. Dual Processor Opteron System
Khepri
1U 2P Opteron
16 GigaBytes RAM, max
Fully Managed
Linux 32 & 64 bit
Windows 32 bit 2000 and .Net Server
Windows 64 bit (when available)
April 16, 2017
Computation Products Group

112. Khepri Block Diagram
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Computation Products Group

113. Khepri Alpha Internal View
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Computation Products Group

114. Availability Solo (AMD Athlon 64) Prototypes are available now
Production planned in Sept. 2003
Serenade (AMD) – Development platform
RDK available now
Production planned for June 2003
Quartet (AMD)
RDK available June 2003
Production planned for Aug. 2003
Khperi (Newisys)
Development units are available now through AMD Beachhead Program
Production Now
April 16, 2017
Computation Products Group

115. Platform Enablement Program
Over the past 24 months, AMD has provided technical design support to over ~50 companies
To date, Newisys has enabled over 17 vendors with their Khepri 2P platform reference design
By Launch (April 2003) there will be 4+ announcements of 4P HPC servers based on AMD Opteron.
By Nov there we be many more vendors with 4P and up to four vendors with 8P SMP/NUMA AMD Opteron platforms.
With the availability of a HyperTransport coherent switch, the NUMA server can grow to 32P and beyond.
April 16, 2017
Computation Products Group

116. 2002-2003 AMD Server Roadmap DP/MP Systems 4Q02 1Q03 2Q03 3Q03 4Q03
Enterprise
SH MP 2.0
SH MP 1.8
SH MP 2.2
SH MP 2.0
SH MP 2.6
SH MP 2.4
Scalable
SH MP 1.6
SH MP 1.8
SH MP 2.2
Basic +
SH MP 1.4
SH MP 1.6
SH MP 1.4
SH MP 2.0
SH MP 1.8
Basic
SH DP 2.0
SH DP 1.8
SH DP 2.4
SH DP 2.2
SH DP 2.0
SH DP 2.4/4200
SH DP 2.6
SH DP 2.4
SH DP 2.2
SH DP 2.6/4500
Value +
SH DP 1.8
SH DP 1.6
SH DP 1.4
SH DP 2.0
SH DP 1.8
SH DP 1.6
SH DP 2.2
SH DP 2.0
SH DP 1.8
SH DP 1.6
SH DP 1.4
THR 2.0/2400+
THR 2.13/2600+
SH DP 1.4/2600
SH DP 1.6/3000
Value
Ultra-Value
THR 1.8/2200+
THR 1.67/2000+
THR 2.0/2400+
THR 1.8/2200+
THR 1.67/2000+
BAR 2.2/2800+
SH DP 1.6
SH DP 1.8
SH DP 1.6
SH DP 1.4
BAR 2.2/2800+
THR 2.13/2600+
THR 2.0/2400+
THR 1.8/2200+
THR 1.67/2000+
BAR 2.2/2800+
SH DP 1.4
THR 2.13/2600+
THR 2.0/2400+
SH DP 1.4
SH DP 1.4/2600
THR 2.13/2600+
AMD Athlon™ MP processor “Thoroughbred” (266MHz FSB)
AMD Opteron processor “SledgeHammer” MP
AMD Athlon MP processor “Barton” (266MHz FSB)
AMD Opteron processor “SledgeHammer” DP
April 16, 2017
Computation Products Group

117. Summary

118. AMD Opteron Processor
Optimized for high performance operation
Chip infrastructure optimized for sub micron process impacting:
Power distribution, Clocking, Circuit design and layout
20-25% better performance per clock than AMD Athlon XP
Smart low-latency memory controller
Branch prediction, Cache and TLB improvements
Advanced clock distribution methods
New operand/address sizes, rather than new instructions
Integrated DDR Memory System Controller
Closing the gap between external memory access and CPU speed
Reduced latency of current Stare of Art (AMD Athlon™ processor)
Greater the bandwidth of current State of Art (AMD Athlon™ system)
Integrated Coherent HyperTransport I/O supporting
High speed peripheral connections - >6.4GB/s throughput
Coherent HyperTransport™ technology to support glueless MP interface
Announce Freq TBD (2.4GHz used elsewhere in prezo, soft peddle this)
Memory controller and other speedups get us 20-25% performance boost over same freq Athlon
April 16, 2017
Computation Products Group

119. Short-term outlook
In the near term, Jerry expects AMD to benefit from the inventory replenishment cycle going on in the semiconductor industry. However, Jerry said the PC business will not benefit from replenishment and will be more reliant on market conditions. “Longer term, we'll be back in command of our destiny if we keep on our roadmaps for technology and product enhancement.”
Jerry said three things will improve AMD’s competitive position going forward:
The addition of a ninth layer of level to the AMD Athlon XP processor, which will give it more headroom on clock speed at any given technology.
The additional L2 cache as AMD moves to 130nm technology
The introduction of the Hammer family of processors
And three factors will contribute to AMD’s future success
Small die through design excellence and architectural superiority
Rapid deployment of SOI (silicon on insulator) technology
AMD’s partnership with UMC, that will help us move to 300mm wafers faster and with less economic impact than we would have accomplished on our own
Long-term outlook
Jerry said he and Hector share two long-term goals for AMD:
To be number one in flash memory by the end of the decade. “We'll be number one because of an enhanced relationship with Fujitsu, our joint venture partner.”
To be number one in microprocessors by the end of the decade for computation, media and information access. Jerry said this includes Alchemy, PC and server processors and the new family of Internet access devices and games, but excludes automotive micro controllers.
Jerry believes AMD has an opportunity to substantially outperform the industry in growth over the balance of this decade. “We are in fast-growing, large markets and we can gain share because of our improving product positioning.

120. Trademark Attribution
©Copyright 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD Arrow Logo, AMD Athlon, AMD Opteron, 3DNow! and combinations thereof are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Consortium. MMX is trademark of Intel Corporation. Other product names used in this presentation are for identification purposes only and may be trademarks of their respective companies.
April 16, 2017
Computation Products Group