1. on behalf of the ATLAS PPS R&D Collaboration
Recent Achievements of the ATLAS Upgrade Planar Pixel Sensors R&D Project
Gianluigi Casse
on behalf of the ATLAS PPS R&D Collaboration
IPRD Oct. 2013, Siena

2. Acknowledgements: PPS Collaboration Members
MPP & HLL Munich (Germany)
Università degli Studi di Udine –
INFN (Italy)
KEK (Japan)
Tokyo Inst. Tech. (Japan)
IFAE-CNM, Barcelona (Spain)
University of Liverpool (UK)
University of Glasgow (UK)
UC Berkeley/LBNL (USA)
UNM, Albuquerque (USA)
UCSC, Santa Cruz (USA)
PPS’s participating members:
CERN
AS CR, Prague (Czech Rep.)
LAL Orsay (France)
LPNHE (France)
University of Bonn (Germany)
HU Berlin (Germany)
DESY (Germany)
TU Dortmund (Germany)
University of Göttingen (Germany)
University of Geneva (CH)
IPRD Oct. 2013, Siena

3. ATLAS Planar Pixel Sensor Project
Prove Planar Technology for all radii of HL-LHC with rad-hard geometries (n-in-n, n-in-p)
Geometry optimization: Slim/Active edges for improved tiling, other optiimisations.
Productions
CiS, MPI-HLL, MICRON, HPK, VTT
Irradiations
Reactor neutrons (Ljubljana)
26 MeV protons (Karlsruhe)
800 MeV protons (Los Alamos)
24 GeV protons (CERN)
70 MeV protons (CYRIC)
26 MeV protons Cyclotron (Birmingham)
Advanced simulations
TCAD packages with radiation parameters
GOALS
Cost reduction
TOOLS
Lab and test beam measurements Radioactive sources
120 GeV π (CERN)
4 GeV e- (Desy)
Eudet telescope
IPRD Oct. 2013, Siena

4. ATLAS Planar Pixel Sensor Project
Silicon Planar technology for ATLAS upgrade pixels??
Have you seen the requirements?
Simone Martini ( c – 1344)
IPRD Oct. 2013, Siena

5. Phase-II Upgrade Pixel Detector
Outer radii: 2 layers
Layer 3 & 4: chip modules
Issues: large scale production of cheap thinned modules
1.7x1015n/cm2; 0.9MGy
Barrel pixels:
5.1 m2 silicon area
Forward pixels
6 disks per side
552 6-chip modules
280 4-chip modules
3.1 m2 silicon area
Issues: large scale production of cheap thinned modules
1.8x1015n/cm2; 0.9MGy
Inner radii: 2 layers
Layer 1: chip modules
Layer 2: chip modules
Issues: radiation damage & small pixels 1.4x1016n/cm2; 7.7MGy
NOTE: ATLAS applies a safety factor of 2 to the estimated doses for detector qualification!
IPRD Oct. 2013, Siena

6. Requirements 2 Inner Barrel layers 2 outer Barrel layers / Disks
Sensors
All sensor materials possible
150 μm silicon or thinner
Pixel size 25 μm x 150 μm
ROIC thickness 150 μm
ToT = 0-8 bits
2x1 and 2x2 chip modules
Data rate as high as 2 Gbit/s per module
2 outer Barrel layers / Disks
Sensor planar n-in-p
Pixel size 50 μm x 250 μm
150 μm thicknesss
ROIC FE-I4X; 2x2cm2 thickness 150 μm
ToT = 4 bits
2x2 FE-I4 (Quad) ~4x4cm2
Data rates of 640 Mbit/s per module
Slide on our plan to make modules at VTT to get a second supplier of modules for the upgrade
Current ATLAS
Phase-II upgrade ATLAS
IPRD Oct. 2013, Siena

7. N-in-N vs N-in-P Issues to compare: Radiation hardness
Double sided process (more expensive, up to 40%)
Pixel can be shifted below guard-rings
Used already widely (ATLAS, CMS, ...)
Single sided process
No backside-alignment needed
More foundries available Easier handling/testing, due to lack of patterned back-side implant
Cost-effective
Danger of sparks between chip and sensor ?
Issues to compare:
Radiation hardness
Prevention of edge sparks
Edge
Cost and handling
IPRD Oct. 2013, Siena

8. Radiation hardness and thickness
It is well documented that radiation hardness is improved (after high fluences) by thinning the sensors. Good for reducing the material. Radiation hardness of n- and p-type substrates and optimal thickness for the pixel layers is investigated.
IPRD Oct. 2013, Siena

9. Radiation hardness of n-in-n and n-in-p sensors
Produced at CiS 285 μm
Irradiated up to 2 · 1016 neq/cm2 Charge as high as 4.2 ke at 1 kV
FE-I4 chip allows for low thresholds of (1-1.5) ke
Hit efficiency fully recoverable by increasing bias voltage
Irradiated with neutrons p to 1016 neq/cm2
Charge exceeds threshold by a factor 2
Hit efficiency 98.1 % in central region (losses in punch through bias)
T. Wittig, “Radiation hardness and slim edge studies of planar n+-in-n ATLAS pixel sensors for HL-LHC”, PIXEL2012
Combined results from MPP and TU Dortmund
C. Gallrapp et al., “Performance of novel silicon n-in-p planar Pixel Sensors ”, Nucl. Instrum. Meth. A679 (2012) 29
IPRD Oct. 2013, Siena
RESMDD, 9-12 October Florence

10. Thin n-in-p Sensors with FE-I4 chip
[KEK/HPK] R. Nagai, et al., "Evaluation of novel KEK/HPK n-in-p pixel sensors for ATLAS upgrade with testbeam", DOI: /j.nima
S. Terzo et al. (MPI Munich), Planar Pixel Sensors meeting, Paris, 30 Sep. 2013
A. Macchiolo, "Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at HL-LHC", PIXEL2012
IPRD Oct. 2013, Siena
RESMDD, 9-12 October Florence

11. Edge sparking issue
At Pixel 2010 T. Rohe reported discharges between sensor and read-out chip.
BCB: No Discharges observed up to 1000 V
Parylene: Tested up to 700 V, no sparks [1]. (Later, other samples, 1000 V)
Silicon adhesive: No discharges observed up to 1000 V
Radiation tolerance might require the application of high bias voltage. This might have the risk of edge sparking due to the proximity of the high voltage edge and the grounded edge of the ROC. Several solutions are envisaged to address this problem both in n-in-n and n-in-p readout geometries.
N-in-n : backplane guard rings
N-in-p :
Coating with parylene
Edge implant on the sensor to reduce the voltage.
Other coatings: glue, silicone adesive, BCB. Different solutions to be implemented at the detector producer or as a post processing step. Optimal solution to be chosen also based on cost and yield.
Y. Unno et al., “Development of novel n+-in-p Silicon Planar Pixel Sensors for HL-LHC”,
IPRD Oct. 2013, Siena

12. Geometry optimisation: adaptive pixel size
Compatible with the FE-I4 floor-plan
Better suited to particular z-regions of the barrel or forward disk/wedges regions
R&D towards strixel solutions
25x500 µm2
50x1000 µm2
100x125 µm2
125x167 µm2
25x1000 µm2
To study: inner pixel size, square pixels in forward direction (low R), strixel solutions ...
Various pixel sizes, punch through or polysilicon biased, AC and DC coupled, Liverpool
IPRD Oct. 2013, Siena

13. Inclined tracks. (High eta).
S. Terzo et al., PPS meeting, Paris,
IPRD Oct. 2013, Siena

14. Testbeam results comparing 50x250 mm2 and 25x500 mm2
Cluster Size X
Cluster Size Y
As expected :
greater number of 2 hit clusters along Y in 500x25 (VTT10)
Increased charge sharing
Minimal change in cluster size in x-direction
(500x25 cluster size is slightly more skewed to 1 than 250x50(VTT5) )
– (Helen look at RMS values)
H. Hayward, "Hiroshima" Symposium – HSTD-9, 2013
IPRD Oct. 2013, Siena

15. Residual, efficiency and resolution – 250x50 vs 500x25
RMS values are approximately (when the resolution from telescope of the DEY testbeam is accounted for) what is expected for pitch/root(12):
500x25 : 500/√12 = 144.3
250x50 : 250/√12 = 72.17
500x25 : 25/√12 = 7.217
250x50 : 50/√12 = 14.43
Width of distribution
500 for 500x25 and about 250 for 250x50
Residuals Y [μm]
IPRD Oct. 2013, Siena
Point out the RMS values are approximately what is expected for pitch/root(12)
Width of distribution (half way up) should be 500 for VTT10 and about 250 for VTT5
Efficiency = %
Efficiency = %
H. Hayward, "Hiroshima" Symposium – HSTD-9, 2013

16. Geometry optimisation: slim or active edges
Reduce need for overlap or inactive gaps (depending on system geometry and location)
IPRD Oct. 2013, Siena

17. Slim or Active Edges: Introduction
Reducing the distance from the cut edge to the active area can be implemented by guard ring design and edge passivation or by active edges.
Two approaches for active edges
DRIE (Deep Reactive Ion Etching) and side
implantation
DRIE trenching, filling and doping by diffusion
Two approaches (with several variants) to edge isolation
SCP: Scribe-Cleave-Passivate Technology
Backplane Guard-Rings (n-in-n only)
Active
edge
Passivated
edge
IPRD Oct. 2013, Siena

18. Active edges with planar n-in-p sensors
- MPP joint project
n-in-p pixels at VTT: active edge process with back-side implantation extended to the edges
100μm thickness
Vbreak~120V
Vdepl ~7-10 V
Charge ~ 6±1 ke
A. Macchiolo, "Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at HL-LHC", PIXEL2012
CCE with 90Sr scans
IPRD Oct. 2013, Siena

19. Active edges with planar n-in-p sensors
FE-I3
MPP - 50 μm edge sensor
Vbias=15 V
FE-I4
MPP μm edge sensor
Vbias=15 V
Edge pixels show the same charge collection properties as the central ones
Plan to study the hit reconstruction efficiency at the edges with test-beam before and after irradiation
A. Macchiolo, "Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at HL-LHC", PIXEL2012
IPRD Oct. 2013, Siena

20. Active Edges Deep trench diffusion (electric field stabilisation)
10 mm width
220 mm depth
Polysilicon filling
IPRD Oct. 2013, Siena

21. Slim Edges: n-in-n Design Approach
Project by TU Dortmund
Guard Rings are shifted beneath the outermost pixels
Least possible inactive edge ∼ 200μm
Less homogeneous electric field, but charge collection dominated by region directly beneath the pixel implant
Approach adopted in IBL
Bottom right: Test design with stepwise shifted pixels, this shows how collected charge is affected due to a less homogeneous electric field when pixels are shifted under the GR’s, bottom left: shows the effect on efficiency for same structure.
A. Rummler, Silicon n-in-n pixel detectors: Sensor productions for the ATLAS upgrades, first slim-edge measurements and experiences with detectors irradiated up to SLHC fluences, 6Th Trento Workshop on Advanced Radiation Detectors
IPRD Oct. 2013, Siena

22. Slim Edges: SCP
Project by SCIPP (UCSC) and NRL Post-Processing approach
SCP: Scribe-Cleave-Passivate
For n-in-p: ALD deposition of alumina
Relies on:
Low damaged sidewall due to cleaving.
Controlled potential drop along sidewall due to fixed interface charge from passivation.
P. Weigell,   "Recent Results of the ATLAS Upgrade Planar Pixel Sensors R&D Project", PIXEL2012
IPRD Oct. 2013, Siena

23. Dry Etch and Alumina Process
Y. Unno, 2013/10/01 PPS meeting at Paris
Similar process developed
By HPK
IPRD Oct. 2013, Siena

24. Geometry optimisation: other design variations
Punch-through or resistor (polysilicon) bias of the pixel matrix from a common rail. Mitigation of the inefficiency induced by the bias dot (or resistor).
IPRD Oct. 2013, Siena

25. FE-I4 Module Hit Efficiencies
Hit efficiency of the module projected in one single pixel cell, Eudet telescope, 120 GeV pions at CERN-SPS (one of many examples from the testbeam activity of PPS groups.
Design of the FE-I4 pixel
F=4x1015 neq cm-2
400 V
Global eff.= 96.5%
F=4x1015 neq cm-2
500V
Global eff.= 96.9%
Main loss of efficiency in the bias dot and in the bias rail  problem is relevant only for perpendicular tracks.
A. Macchiolo, "Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at HL-LHC", PIXEL2012
IPRD Oct. 2013, Siena

26. Bias Grid Design
To overcome the efficiency loses in the punch through structure for perpendicular tracks, different designs are under investigation: “Bias rail” is a metal over insulator, no implant underneath
Dortmund (right)
Bias rail routed differently 2 alternative designs
KEK (below)
PolySilicon resistor (encircling pixel implant) 3 different designs
Liverpool (CERN Pixel V mask, mentioned before)
PolySilicon resistor (above pixel implant)
IPRD Oct. 2013, Siena

27. Summary
The ATLAS Inner Tracker at the HL-LHC will require a whole new detector, with pixel sensors covering an area exceeding 8 m2. Planar pixels are the obvious solution for most of the layers. The PPS project is making exciting progresses in the various issues posed by this extremely demanding detector. LIKE:
Radiation hardness
Diode geometry (n- or p-type substrates)
Study of different pixel geometries that could be part of the ATLAS ITK
Reduced edges
Quad detectors (not mentioned here, at the moment the likely choice for modules)
Cost reduction
IPRD Oct. 2013, Siena

28. Summary
The PPS groups use simulation, laboratory measurements and test beams to design and test the advanced solutions proposed. A huge effort is performed and here I only mentioned a few highlights of the common activity.
IPRD Oct. 2013, Siena