1. CSCE 212 Chapter 3: Arithmetic for Computers Instructor: Jason D. Bakos

2. CSCE 212 2 Lecture Outline Review of topics from 211 Overflow Binary Multiplication Binary Division IEEE 754 Floating Point Floating-Point Addition and Multiplication MIPS Floating-Point

3. CSCE 212 3 Review Binary and hex representation Converting between binary/hexidecimal and decimal Two’s compliment representation Sign extention Binary addition and subtraction

4. Addition CSCE 212 4

5. CSCE 212 5 Lecture Outline Review of topics from 211 Overflow Binary Multiplication Binary Division IEEE 754 Floating Point Floating-Point Addition and Multiplication MIPS Floating-Point

6. CSCE 212 6 Overflow Overflow for unsigned addition –Carry-out Overflow for unsigned subtraction –No carry-out Overflow for signed Overflow causes exception –Go to handler address 80000080 –Registers BadVAddr, Status, Cause, and EPC used to handle SPIM has a simple interrupt handler built-in that deals with interrupts OperationOperand AOperand BResult A+BPositive Negative A+BNegative Positive A-BPositiveNegative A-BNegativePositive

7. CSCE 212 7 Overflow Test for signed ADD overflow: addu$t0,$t1,$t2# sum but don’t trap xor$t3,$t1,$t2# check if signs differ slt$t3,$t3,$zero# $t3=1 if signs differ bne$t3,$zero, No_OVF xor$t3,$t0,$t1# signs of operands same, compare sign of result slt$t3,$t3,$zero bne$t3,$zero,OVF Test for unsigned ADD overflow: addu$t0,$t1,$t2# sum but don’t trap nor$t3,$t1,$zero# invert bits of $t1 (-$t1–1), 2 32 -$t1-1 sltu$t3,$t3,$t2# 2 32 -$t1-1 < $t2, 2 32 -1 < $t1+$t2 bne$t3,$zero,OVF

8. CSCE 212 8 Lecture Outline Review of topics from 211 Overflow Binary Multiplication Binary Division IEEE 754 Floating Point Floating-Point Addition and Multiplication MIPS Floating-Point

9. CSCE 212 9 Binary Multiplication 1000 x 1001 1000 0000 1000 1001000 multiplicand multiplier product

10. CSCE 212 10 Binary Multiplication

11. CSCE 212 11 Binary Multiplication works with signed but must sign extend shifts

12. CSCE 212 12 Multiplication Example multiplicand register (MR)product register (PR)next actionit 10010000 0101LSB of PR is 1, so PR[7:4]=PR[7:4]+MR 1 10011001 0101shift PR1 10010100 1010LSB of PR is 0, so shift2 10010010 0101LSB of PR is 1, so PR[7:4]=PR[7:4]+MR 3 10011011 0101shift PR3 10010101 1010LSB of PR is 0, so shift4 10010010 1101PR is 45, done!X

13. CSCE 212 13 Faster Multiplication

14. CSCE 212 14 Lecture Outline Review of topics from 211 Overflow Binary Multiplication Binary Division IEEE 754 Floating Point Floating-Point Addition and Multiplication MIPS Floating-Point

15. CSCE 212 15 Binary Division

16. CSCE 212 16 Binary Division

17. CSCE 212 17 Binary Division For signed, convert to positive and negate quotient if signs disagree

18. CSCE 212 18 Division Example divisor register (DR)remainder register (RR)next actionit 01000000 1011shift RR left 1 bit0 01000001 0110RR[7:4]=RR[7:4]-DR1 01001101 0110RR<0, so RR[7:4]=RR[7:4]+DR1 01000001 0110shift RR to left, shift in 01 01000010 1100RR[7:4]=RR[7:4]-DR2 01001110 1100RR<0, so RR[7:4]=RR[7:4]+DR2 01000010 1100shift RR to left, shift in 02 01000101 1000RR[7:4]=RR[7:4]-DR3 01000001 1000RR>=0, so shift RR to left, shift in 13 01000011 0001RR[7:4]=RR[7:4]-DR4 01001111 0001RR<0, so RR[7:4]=RR[7:4]+DR4 01000011 0001shift RR to left, shift in 04 01000110 0010shift RR[7:4] to right 01000011 0010done, quotient=2, remainder=3

19. CSCE 212 19 Lecture Outline Review of topics from 211 Overflow Binary Multiplication Binary Division IEEE 754 Floating Point Floating-Point Addition and Multiplication MIPS Floating-Point

20. CSCE 212 20 Fixed-Point Need a way to represent fractional numbers in binary Fixed-point –Assume a decimal point at some location in a value: –Example: 6-bit (unsigned) value = 1x2 1 + 0x2 0 + 1x2 -1 + 1x2 -2 + 0x2 -3 + 1x2 -4 For signed, use two’s compliment –Range = [-2 N-1 /2 M, 2 N-1 /2 M – 1/2 M ] –For above, [-2 5 /2 4, 2 5 /2 4 -1/2 4 ]  [-2,2-1/16] 10.1101

21. CSCE 212 21 Precision Assume we have 4 binary digits to the right of the point… –Convert.8749 to binary… –.1101 =.8125 –Actual value – represented value =.0624 (bound by 2 -4 )

22. CSCE 212 22 Floating Point Floating point represent values that are fractional or too large –Expressed in scientific notation (base 2) and normalized –1.xxxx 2 * 2 yyyy –xxxx is the significand (fraction) and yyyy is the exponent –First bit of the significand is implicit –Exponent bias is 127 for single-precision and 1023 for double-precision IEEE 754 standard –Single-precision (2x10 -38 to 2x10 38 ) bit 31: sign of significand bit 30..23 (8) exponent bit 22..0 (23) significand –Double-precision (2x10 -308 to 2x10 308 ) Significand is 52 bits and the exponent is 11 bits Exponent => range, significand => precision To represent: –zero: 0 in the exponent and significand –+/- infinity: all ones in exponent, 0 in significand –NaN: all ones in exponent, nonzero signficand

23. CSCE 212 23 Conversion To convert from decimal to binary floating-point: –Significand: Use the iterative method to convert the fractional part to binary Convert the integer part to binary using the “old-fashioned” method Shift the decimal point to the left until the number is normalized Drop the leading 1, and set the exponent to be the number of positions you shifted the decimal point Adjust the exponent for bias (127/1023) When you max out the exponent, denormalize the significand

24. IEEE 754 CSCE 212 24

25. CSCE 212 25 Lecture Outline Review of topics from 211 Overflow Binary Multiplication Binary Division IEEE 754 Floating Point Floating-Point Addition and Multiplication MIPS Floating-Point

26. CSCE 212 26 Floating-Point Addition Match exponents for both operands by un-normalizing one of them –Match to the exponent of the larger number Add significands Normalize result Round significand

27. CSCE 212 27 Example Assume 11-bit limited representation: –1 bit sign bit –6 bit significand (precision 2 -6 = 0.0156) –4 bit exponent (bias 7) range 1 x 2 -7 (7.8 x 10 -3 ) to 1.111111 x 2 8 (5.1 x 10 2 ) (assuming no denormalized numbers)

28. CSCE 212 28 Accurate Arithmetic Keep 2 additional bits to the right during intermediate computation –Guard, round, and sticky Worst case for rounding: –Actual number is halfway between two floating point representations –Accuracy is measured as number of least-significant error bits (units in the last place (ulp)) IEEE 754 guarantees that the computer is within.5 ulp (using guard and round)

29. CSCE 212 29 Floating-Point Addition Hardware

30. CSCE 212 30 Floating-Point Multiplication Un-bias and add exponents Multiply significands –Move point Re-normalize Set sign based on sign of operands

31. CSCE 212 31 Lecture Outline Review of topics from 211 Overflow Binary Multiplication Binary Division IEEE 754 Floating Point Floating-Point Addition and Multiplication MIPS Floating-Point

32. CSCE 212 32 MIPS Floating-Point $f0 - $f31 coprocessor registers –Used in pairs for doubles Arithmetic: [add | sub | mul | div].[s | d] Data transfer: lwc1, swc1 (32-bits only) Conditional branch: –c.lt.[s | d] (compare less-than) –bclt (branch if true), bclf (branch if false) Register transfer: –mfc1, mtc1 (move to/from coprocessor 1, dest. is first)