1. SVT INFN LNF - 28 Marzo 2007Alberto Annovi1 STARS: Supercomputers for Trigger Analysis and Real-time Selections Alberto Annovi Istituto Nazionale di Fisica Nucleare Laboratori Nazionali di Frascati Proposal for Ideas - FP VII

2. SVT INFN LNF - 28 Marzo 2007Alberto Annovi2 Outline STARS Trigger: we always need more power! CDF trigger problems/upgrades/solutions More for the next future? SVT & AM could survive after CDF at both level 1 (CMS @SLHC? SLIM5) and level 2 (ATLAS?) other applications?

3. SVT INFN LNF - 28 Marzo 2007Alberto Annovi3 STARS STARS: Supercomputers for Trigger Analysis and Real-time Selections Current and future (HEP) experiments look for extremely rare processes hidden by severe background conditions. The trigger dramatically affects our ability to extract these tiny signals from the huge backgrounds. export the successful parallel CDF trigger approaches to new experiments  Challenging: competition with Farm approach New experiments need powerful exclusive, high resolution triggers! The trigger cannot be “inclusive, low resolution” any more!  very large comupting power needed  time is critical

4. SVT INFN LNF - 28 Marzo 2007Alberto Annovi4 Looking for very rare phenomena Hans Bethe: “Young man, if the cross section is so low, increase the luminosity !” @hadronic collider not only the luminosity has to be increased, but also the bandwidth, the purity … From collision point all the way to PRL editors Trigger is a critical part of this process: errors cause not-recoverable losses!

5. SVT INFN LNF - 28 Marzo 2007Alberto Annovi5 CDFTrigger power: (1) TTT: the displaced TrkTrigger but also Terrific Tracking (@ L1/L2 ) Run I collected O(1) B s --> D s  (all D s modes) Run II collected ~2000 B s --> D s  (D s -->  -->K + K - ]  ) Compare with only 10x integrated luminosity! The trigger had a much bigger impact than Tevatron upgrade!!! Without SVTWith SVT RUN I RUN II

6. The SVT advantage: 3 orders of magnitude B 0  had + had Trigger KsKs D0D0 S. Donati, M. Morello, G. Punzi, D. Tonelli, G. Volpi M hh (GeV) L3 plot 2001 SVT TDR 1995

7. SVT INFN LNF - 28 Marzo 2007Alberto Annovi7 SVT: many different boards  2 years for upgrade  PULSAR x12 wedges Hit Finder AM Sequencer AM Board Detector Data Hits Super Strip Matching Patterns Roads L2 CPU AM++ Hit Buffer Tracks + Corresponding Hits Roads + Corresponding Hits Track Fitter AMSRW HB++ TF++ Powerful flexible PULSARS Just add Firmware GF ++ P. Catastini et al.

8. SVT INFN LNF - 28 Marzo 2007Alberto Annovi8 On the opposite side: FPGA for the same AMchip P. Giannetti et al. “A Programmable Associative Memory for Track Finding”, Nucl. Intsr. and Meth., vol. A413/2- 3, pp.367-373, (1998). AM chips from 1992 to 2005 (90’s) Full custom VLSI chip - 0.7  m (INFN-Pisa) 128 patterns, 6x12bit words each 32k roads / wedge F. Morsani et al., “The AMchip: a Full-custom MOS VLSI Associative memory for Pattern Recognition”, IEEE Trans. on Nucl. Sci., vol. 39, pp. 795-797, (1992). In the middle: Standard Cell 0.18  m (INFN Ferrara, Pisa)  5000 pattern/chip AMchip L. Sartori, A. Annovi et al., “A VLSI Processor for Fast Track Finding Based on Content Addressable Memories”, IEEE Transactions on Nuclear Science, Volume 53, Issue 4, Part 2, Aug. 2006 Page(s):2428 - 2433 NEXT: NEW VERSION For both L1 & L2

9. SVT INFN LNF - 28 Marzo 2007Alberto Annovi9 Muon acceptance Inclusive  =31% Exclusive  =63% Electron acceptance Exclusive  =64% Inclusive  =36% Release lepton quality cuts --> gain acceptance x2 Control rate with jet/MET requirements --> exclusive triggers Need high-quality jet/MET trigger --> under upgrade! CDFTrigger power: (2) also Terrific Calorimeter selection (@L2 ) WH--> lvbb triggers

10. SVT INFN LNF - 28 Marzo 2007Alberto Annovi10 Example: New exclusive WH-> evbb trigger M. Casarsa et al. (in progress) A real >80% efficient trigger with low rate @ peak lumi Using L2 clustering upgrade Tools L1_ET TOW >10 GeV L1_MET >15 GeV L2_MET > 20 GeV L2_Et e > 8 GeV L2_2Jet> 12 GeV

11. SVT INFN LNF - 28 Marzo 2007Alberto Annovi11 CDF LVL2 Calo upgrade Need a cone algorithm! MET>15 GeV Better Resolution & Efficiency Turn on for MET 20 32 L3MET Better jet Resolution 15<ET<18 L2cone Pacman Same Pulsars Same mezzanines

12. SVT INFN LNF - 28 Marzo 2007Alberto Annovi12 CPU & STARS LHC HLT strategy: we “JUST” buy CPUs and write software… CPUs are flexible but missing time can freeze the flexibility! SVT approach: (1st STARS prototype born for a tough JOB) split the algorithm among different technologies VLSIs (AM chip), FPGAs (Pulsars+mezzanines), CPUs Use the appropriate tool i.e. no time waste! Proton-antiproton collision point B decay vertex Impact parameter ( d ) Transverse view ~ 1 mm We will also buy STARS blocks (Pulsars & AM chips) & write firmware + software

13. SVT INFN LNF - 28 Marzo 2007Alberto Annovi13 SVT Fast Track (FTK) Gr V for L2 @ LHC SLIM5 Gr V for L1 Next challenge is silicon tracking at both Level 1 & Level 2 LHC What next ? Ideas from P. Giannetti M. Dell’Orso L. Ristori G. Punzi A. Annovi

14. SVT INFN LNF - 28 Marzo 2007Alberto Annovi14    CMS: 30 minimum bias events + H->ZZ->4   Tracks with P t >2 GeV Help!  30 minimum bias events + H->ZZ->4  Tracks with P t >2 (or Pt>1) GeV for b/  -tagging @ level 2; P t >5 GeV for leptons @ level 1 Where is the Higgs?   FTK  A powerful tool Where is the Higgs? Online tracking: a tough problem

15. SVT INFN LNF - 28 Marzo 2007Alberto Annovi15 Where could we insert FTK? PIPELINE LVL1 CALO MUON TRACKER Buffer Memory ROD Buffer Memory FE Raw data ROBs 2 nd output 1 st output Fast Track + few (Road Finder) CPUs Fast Track + few (Road Finder) CPUs Track data ROB Track data ROB high-quality tracks: Pt>1 GeV Ev/sec = 50~100 kHz Very low impact on DAQ No change to LVL2 Fast network connection CPU FARM (LVL2 Algorithms)

16. SVT INFN LNF - 28 Marzo 2007Alberto Annovi16 B-tagging @ ATLAS (w/o & w/ FTK) LVL2 EF offline ATLAS T&P march 2007 LVL2 vs offline 10 times less rejection EF vs offline difference being investigated with Fast-TracK offline b-tag performances @LVL2 With FTK use offline-quality tracks for all triggers, e.g. sophisticated  triggers

17. SVT INFN LNF - 28 Marzo 2007Alberto Annovi17 FTKsim versus iPatRec - Resolution CurvatureImpact Parameter  Cot(  ) 1/GeV cm rad M. Dell’Orso, F. Crescioli, G. Punzi, G. Volpi, P. Giannetti et al. (Pisa-Chicago) On going Real Time Tracking & b/  /Bs tagging performance study

18. SVT INFN LNF - 28 Marzo 2007Alberto Annovi18 Trigger xsec (nb) (MSSM Higgs) Selected triggers with tracks/jets Di Muon trigger (J/Psi, Bs->  ) L1 two muons Pt>1.5 L2 Pt>2 && Dynamical Prescale will use SVT in the future Z -> bb trigger (bjet calibration, top mass) L1 jet5, trk5.5, trk2.5 L2 two trk ip>160  m, ~ same z vertex two jet5 Rate Bs->   with SVT Hadronic di tau L1 2jet5, 2trk6 L2 2jet10, 2trk10 High Pt electron (W, Z, W+H, top) L1 EM8, trk8 L2 EM16, trk8 Luminosity (xE30 cm -2 s -1 )

19. SVT INFN LNF - 28 Marzo 2007Alberto Annovi19 Note limited rejection power (slope) without tracker information CMS-DAQ TDR F. Palla Proposal (LECC06 workshop) 26 cm 34 cm 42 cm 50 cm SLHC: 100-400 Minimum Bias events/bx (12.5 ns - 50ns) occupancy degrades performance of trigger algorithms Implies raising E T thresholds or use tracks ~2000 tracks/bx in |  |<1.5 But only a few ‰ have p T >5 GeV/c This plan match with AMchip features!!! 4 pixel layer CMS Muon Rate at L =10 34 cm -2 s -1 Current CMS pixels have links for L1

20. SVT INFN LNF - 28 Marzo 2007Alberto Annovi20 AMchip receives up to 6 parallel buses for 6 layers at frequency: AMchip now: 50 MHz (Level 2) Next generation: 100 MHz or more Goal: use SAME CHIP for Level 2 & 1 1 AM for each enough-small  space-time Patterns Hits: position+time stamp All patterns inside a single chip N chips for N overlapping events identified by the time stamp Main problem: AM input Bandwidth, even if powerful: >10 Gbits/sec  divide the detector in thin  sectors. Each AM searches in a small  Same blocks --> different applications x80 wedges Similar use (L1 tracking) for CMS (F.Palla proposal) SLIM5 SuperB? (F. Forti, M. Giorgi et al.)

21. SVT INFN LNF - 28 Marzo 2007Alberto Annovi21 The trigger harmonizes the experiment  exclusive selections The power of a detector can cover the weakness of another  1.Weak  coverage?  use only tracking & calorimeter to release muon identification CDF: top muons 2. Trigger power: no need for trigger dedicated detectors. The trigger MUST not constrain the detector design! An alternative CMS L1 track trigger Double layers more material to simplify the the trigger. Is this a good idea?

22. SVT INFN LNF - 28 Marzo 2007Alberto Annovi22 AM Board? Detector Data towers Matching Patterns Recover Full resolution data L1?L2 CPU Full resolution jet/electrons ? AM++? Hit Buffer Same blocks --> different applications SVT for Calo? MEG proven SVT Track Fitter algorithm could do offline gamma reconstruction with 800 phototubes. Can we use “STARS” for offline-quality calorimeter reconstruction? Same structure Similar Hardware To be studied… @ LVL1 ?!? GigaFitter

23. SVT INFN LNF - 28 Marzo 2007Alberto Annovi23 Same blocks --> different applications AM: massive parallelism in data correlation searches coincidence/anticoincidence of up to 12 measurements! For example: Muon: T1&T2&T3&not(Ecal)&not(Hcal)&M1&M2&M3&M4&M5 LHCB CDF

24. SVT INFN LNF - 28 Marzo 2007Alberto Annovi24 Creare un gruppo di esperti (ampio campo di conoscenze per algoritmi, trigger, fisica, diverse tecnologie e loro interconnessioni: FPGA, standard cell, CPUs, links) che possa in parte realizzare (CDF- FTK) in parte favorire la crescita delle idee esposte con: 1.massa critica sufficiente 2.finestra temporale sufficientemente ampia Cosa vogliamo fare con i fondi Ideas??

25. SVT INFN LNF - 28 Marzo 2007Alberto Annovi25 1.Complete CDF: Hardware/Trigger studies/Analysis 2.FTK @ ATLAS (ongoing upgrade proposal Pisa/Chicago +….): Physics case/Hardware/Analysis (to be approved) 3.New AM chip for level1 – level2 Favor other project development for upgrades & other CMS – SuperB ….. sharing: 1.Hardware (in particular new AM chip) 2.software tools (simulation/diagnostic-control-config.) 3.Trigger ideas STARS could generate new Ideas projects: Brain study – Routers – security (Cooperation) STARS CMS? SuperB L1? Brain Study Routers- Security? LHCB? Cosa vogliamo fare con i fondi Ideas?? Add your idea here!!!

26. SVT INFN LNF - 28 Marzo 2007Alberto Annovi26 CHI SIAMO e Richieste VII FP 1.FRASCATI: A. Annovi (art. 36-PI, SVT upgrade ex-project leader), S. Torre (Ass. Ric., SVT operations manager) 2.PISA: P. Giannetti (Dir. Ric.), M. Dell’Orso (Prof. Ass.), L. Sartori (M. Curie OIF, AM chip designer, L2 cal. upgrade technical coordinator) 3.FERRARA: storica collab. Ape-CDF per AM standard cell. F.Schifano (RU), R. Tripiccione (Prof. Ord.) – Invitato a partecipare il gruppo Babar – speriamo che accetti IDEAS tot 400 keuro/year (5 years): 1.Man Power for 5 year: Frascati PI + 2 art. 23 – Pisa 1+1/2 art. 23 – Ferrara 1+1/2 art. 23 = 56 + 44 * 5 = 275 + 55 (20% over.) = 330 keuro 2.70 keuro/year AM chip subcontractors. Prototype using MPW with very challenging technology (~350 keuro tot) 3.Missioni/conferenze/… = 0 euro

27. SVT INFN LNF - 28 Marzo 2007Alberto Annovi27 BACKUP SLIDES

28. SVT INFN LNF - 28 Marzo 2007Alberto Annovi28 Tracking processing time With Associative Memory processing time proportional to occupancy 10x luminosity --> 10x AM hardware With CPUs processing time proportional to combinatorial harder to predict! Hardware needs increase exponentially with luminosity! 10x luminosity --> e 10 times CPUs….

29. SVT INFN LNF - 28 Marzo 2007Alberto Annovi29 Layer 0: ~25 fibers bringing ~40 Hits/12 ns............ AM EV0 AM EV1 AM EV40...... 1 Hit/10 ns 1 FIFO/ fiber From other layers From other layers From other layers Distribute hits into different sets of registers depending on Event # FPGA The switch board 1 switch / layer layer 0 AM latency = passthrough time (10bx?) + # hits * clock period AM clock (>100MHz) Here is were # of hits and its fluctuations matter

30. SVT INFN LNF - 28 Marzo 2007Alberto Annovi30 VIRTEX 5: 65 nm- 550 MHz devices XC5VSX95T: 160 x 46 CLB Array (Row x Col) Each Slice: 1.4 6-input Luts or RAM or SR 2.4 FFs 3.Wide MUXs 4.Carry logic 160 46 244 39kbits BlockRams or Fifos+ 640 DSP Slices (organized in columns) ~1200 euro

31. SVT INFN LNF - 28 Marzo 2007Alberto Annovi31 B-tagging @ ATLAS (w/o & w/ FTK) LVL2 EF offline ATLAS T&P march 2007 LVL2 vs offline difference 10 times less rejection EF vs offline difference being investigated with Fast-TracK offline b-tag performances @LVL2 ATLAS TP 31/3/2000 0.6 100 10 1000 bb RuRu

32. SVT INFN LNF - 28 Marzo 2007Alberto Annovi32 L=2x10 33 cm -2 sec - 1 HLT  selection @ CMS H(200,500 GeV)   1,3h ± + X 0.4 0.5 0.6 0.7 0.8 0.9 1. 0 0.02 0.06 0.1 0.14  (QCD 50-170 GeV)  (H(200,500 GeV)   1,3h+X) m H =500 m H =200 TRK tau on first calo jets Pix tau on first calo jet Staged-Pix tau on first calo jet TRK tau on both calo jets Calo tau on first jet 0.0070.004 Efficiency & jet rejection could be enhanced by using tracks before calorimeters.

33. SVT INFN LNF - 28 Marzo 2007Alberto Annovi33 bbH/A  bbbb ATLAS-TDR-15 (1999) M A (GeV) tan  200 Analysis: 4 b-jets |  j |<2.5 P T j > 70, 50, 30, 30 GeV efficiency 10% Effect of trigger thresholds (before deferrals) ATLAS + FTK triggers 13%3b leading3J + SE200 8%3 b-tags MU6  + 2J Effic.LVL2LVL1 As efficient as offline selection: full Higgs sensitivity ATL-COM-DAQ-2002-022

34. SVT INFN LNF - 28 Marzo 2007Alberto Annovi34 **** di-muon triggers for rare decays LVL1: 2  RoI p T (  ) > 6GeV (~500 Hz @ L=10 33 cm -2 s -1 ) LVL2:  Confirm each  RoI from LVL1  In precision muon chambers  Combine  with Inner Detector track  Mass cut 4 GeV < M(  )< 6 GeV EF: Refit ID tracks in Level-2 RoI Decay vertex reconstruction Transverse Decay length cut: L xy > 200  m Efficiency estimation L2/EF: bb   +  - for both  p T >6 GeV –70% of B   +  - –(60% of B  K *  +  - ) Online reconstruction of di-  mass, (MeV) B  K *  +  - B   +  - Not normalized BEAUTY 2006 talk

35. SVT INFN LNF - 28 Marzo 2007Alberto Annovi35 3cm 15cm 150cm Outer drift chamber Silicon  strip detector Silicon close-up Impact parameter Beam spot 1mm Zoom-in Input (every Level 1 accept): XFT trajectories silicon pulse height for each channel Output (about 20 microseconds later): trajectories that use silicon points r-  tracks impact parameter:  (d)=35  m SVT @ CDF Level 2 -> next generation SVT @ Level 1 AM algo

36. SVT INFN LNF - 28 Marzo 2007Alberto Annovi36 Lepton triggers @ level 1 match between a muon stub or calorimeter signal with XFT track 80 140 200 Luminosity (xE30 cm -2 s -1 ) Level 1 rate (Hz) 600Hz Level 1 mu Pt>4 GeV

37. SVT INFN LNF - 28 Marzo 2007Alberto Annovi37 The Event Pattern matching in CDF (M. Dell’Orso, L.Ristori 1985 -..)... The Pattern Bank The pattern bank is flexible set of pre-calculated patterns: can account for misalignment changing detector conditions beam movement …

38. SVT INFN LNF - 28 Marzo 2007Alberto Annovi38 Dedicated device: maximum parallelism Each pattern with private comparator Track search during detector readout If you can read it out you can track it! AM: Associative Memory Bingo scorecard

39. SVT INFN LNF - 28 Marzo 2007Alberto Annovi39 Associative Memory (AM) for pattern matching M. Dell'Orso and L. Ristori, “VLSI structures for track finding”, Nucl. Instr. and Meth., vol. A278, pp. 436-440, (1989). 1 register 1 comparator 1 match FF / layer / pattern

40. SVT INFN LNF - 28 Marzo 2007Alberto Annovi40 5 CLB (come Block RAM): 32 into each column x 20 columns DSP SliCEs

41. SVT INFN LNF - 28 Marzo 2007Alberto Annovi41 SVT FiFo 35 MHz II FiFo 70 MHz Lay0-Ram or SRLay1- Ram or SRLay2- Ram or SRLay3-Ram or SRLay4-Ram or SRXFT-Ram or SR Comb - FiFo 7 Mult+7  6 Mult+6  37 DSP slices/Equation. For 6 equations 37x6= 222 DSP slices Choose best chi**2 Each equation is calculated 6 times (all layers and 1 SI-missing) 6 input LUT Inside Slices BLock RAMs 6 fit in parallelo/Wedge Choose the best chi**2

42. SVT INFN LNF - 28 Marzo 2007Alberto Annovi42 FPGA 40 JTAG 4 wedge connectors on each mezzanine  possible up to 6x4=24 fits in parallel 3 mezzanines = 12 wedges 4 th mezzanine  large memory for non-linearity corrections

43. SVT INFN LNF - 28 Marzo 2007Alberto Annovi43 1995: 0.35  FPGA same AM than 0.7  full custom Very regular layout and routing. 95% used logic Same timing performances of the full custom chip! Since then Cam has been introduced into FPGA. We use FPGA AM in the Road warrior to delete SVT ghosts (two candidate tracks differing only for empty layers Pattern

44. SVT INFN LNF - 28 Marzo 2007Alberto Annovi44 AM projects SVT: Silicon Vertex Trigger @ CDF (L. Ristori et al.) first AM application extremely successful B s mixing, A CP B->hh’, Z->bb, bbH->4b proven to be easy to upgrade (1-2 years turn around time) FTK: FastTracK @ ATLAS (preparing a proposal: P.Giannetti-Pisa, M. Shochet, YK Kim- Chicago, T. Liss - Illinois et al.) Full tracker reconstruction @ L2 @ full L1 out rate 100kHz Offline quality (see next slide) and efficiency ???: L1 tracking @ CMS (F.Palla proposal) tracking at 80MHz momentum measurement with a few (4?) “pixel” layers SLIM5: L1 tracking @ SuperB (F. Forti, M. Giorgi et al.) R&D to develop MAPS sensor integrated with AM trigger

45. SVT INFN LNF - 28 Marzo 2007Alberto Annovi45 AM synergy Several AM based projects --> great advanteges: share hardware: develop a single new AMchip we are applying for CE funds for a prototype share expertise: many people are/have been involved in SVT or FTK share tools: e.g. trigger simulation share mantainance (spares/diagnostics...) makes the project easier and cheaper We can help providing training and tools. To start this very “rewarding” business: you will need a smaller motivated group in charge of the project!

46. SVT INFN LNF - 28 Marzo 2007Alberto Annovi46 How to process all data @ bx rate? 1.Take advantage of AM input bandwidth Currently 50 MHz (hits/sec/layer) Hits for different layers are loaded in parallel Next version > 100MHz (90nm tech. & pipelining) 2.Parallelize by  sectors ~80 detector  sectors are processed in parallel implies a minimum Pt threshold (e.g. >5 GeV) 3.Parallelize different events for each sector 40 AMchips process 40 events in parall. need switch boards housing ~40 AMchips with FPGAs used as data switch for AMchips Caveat: need to take care of # of hits fluctuations

47. SVT INFN LNF - 28 Marzo 2007Alberto Annovi47 switch board numbers All info here TBC with simulation and R&D! 80 switch boards 1 /  -sector 80 fibers / board assume 5Gbps each 40 AMchip / board now we can fit 32 AMchips in one 4 th of a 9U VME board 4 FPGA switches (1/layer) Each receiving ~20 fibers, i.e. ~100Gbps 40 outputs: one per Amchip Possible with today’s FPGAs 32 AMchips

48. SVT INFN LNF - 28 Marzo 2007Alberto Annovi48 The CDF Tracker TIME OF FLIGHT B field = 1.4 T Longitudinal view Transverse view

49. SVT INFN LNF - 28 Marzo 2007Alberto Annovi49 CDF Trigger Architecture Drift chamber tracking Lepton reco/track matching … Silicon tracking Secondary vertex selection … CPU farm Full event reconstruction with speed optimized offline code Level 1 pipeline: 42 clock cycles Level 1 Trigger L1 Accept Level 2 Trigger Level 2 buffer: 4 events L2 Accept DAQ buffers L3 Farm Level 1 7.6 MHz Synchromous Pipeline 5.5  s Latency 30 kHz accept rate Level 2 Asynchromous 2 Stage Pipeline 20  s Latency 1000 Hz accept rate Mass Storage (~100 Hz) Raw data, 7.6 MHz Crossing rate SVX read out after L1 SVT here XFT here

50. SVT INFN LNF - 28 Marzo 2007Alberto Annovi50 Hadronic B decays L1 Two XFT tracks P t > 2 GeV; P t1 + P t2 > 5.5 GeV  < 135° Two body decaysMany body decays L2 Validation of L1 cuts with  >20° 100  m<d 0 <1mm for both tracks Lxy > 200  m d 0 (B)<140  m Validation of L1 cuts with  >2° 120  m<d 0 <1mm for both tracks Lxy > 200  m d 0 (B)<140  m B -> h h’B s mixing Two trigger paths Essential for Bs mixing measurement!

51. SVT INFN LNF - 28 Marzo 2007Alberto Annovi51 1.Find low resolution track candidates called “roads”. Solve most of the pattern recognition 2.Then fit tracks inside roads. Thanks to 1 st step it is much easier Super Bin (SB) Too much large AM  Tracking in 2 steps OTHER functions are needed inside SVT: Hit Buffer + Track fitter + Hit Finder

52. SVT INFN LNF - 28 Marzo 2007Alberto Annovi52 SVT Performance -500 -250 0 250 500 (  m) 35  m  33  m resol  beam   = 48  m SVT Impact parameter 90% efficient given a fiducial offline track with SVX hits in 4 layers

53. SVT INFN LNF - 28 Marzo 2007Alberto Annovi53 Promise is promise What we promised…. From SVT TDR (’96) using offline silicon hits and offline CTC tracks  ~ 45  m

54. SVT INFN LNF - 28 Marzo 2007Alberto Annovi54 SVX only  Good tracks from just 4 closely spaced silicon layers  I.p. as expected due to the lack of curvature information impact parameter distribution  ~ 87  m Silicon only no XFT

55. SVT INFN LNF - 28 Marzo 2007Alberto Annovi55 SVT Upgrade (done, fall 2005) 0 20 60 100 140 180 Luminosity (xE30) original system upgraded system Timing (  s) L1 bandwidth 18kHz -> 30kHz Now stable w.r.t luminosity Need to process more complex events in less time Same architecture as original system Better pattern recognition resolution New AM chip 32K  512K patterns fewer combinations/road Faster components Use custom but general purpose Pulsar boards http://hep.uchicago.edu/~thliu/projects/Pulsar/ Short development time Parassitic test & validation of boards Take good data @ high lumi & more data @ low lumi NSS2005 Conf. Rec. Vol.1, 603

56. SVT INFN LNF - 28 Marzo 2007Alberto Annovi56 SVT flexibility for new ideas SVT designed to be flexible programmable patterns Look Up Tables & FPGAs modular system Pulsar programmable board with SVT connectors implement new functions in ~ a few months Design system for easy testing Extensive on-crate monitoring during beam

57. SVT INFN LNF - 28 Marzo 2007Alberto Annovi57 Track data ROB Track data ROB Raw data ROBs ~Offline quality Track parameters ~75 9U VME boards – 4 types SUPER BINS DATA ORGANIZER ROADS ROADS + HITS EVENT # N PIPELINED AM HITS DO-board EVENT # 1 AM-board 2 nd step: track fitting Inside Fast-Track Pixels & SCT Data Formatter (DF) 50~100 KHz event rate RODs cluster finding split by layer overlap regions RW Few CPUs NEW S-links

58. SVT INFN LNF - 28 Marzo 2007Alberto Annovi58 CurvatureImpact Parameter  Cot(  ) Z Particle Type FTKsim versus iPatRec – Efficiency M. Dell’Orso, F. Crescioli, G. Punzi, G. Volpi, G. Usai

59. SVT INFN LNF - 28 Marzo 2007Alberto Annovi59  x i Non-linear geometrical constraint for a circle: F(x 1, x 2, x 3, …) = 0 But for sufficiently small displacements: F(x 1, x 2, x 3, …) ~ a 0 + a 1  x 1 + a 2  x 2 + a 3  x 3 + … = 0 with constant a i (first order expansion of F) From non-linear to linear constraints

60. SVT INFN LNF - 28 Marzo 2007Alberto Annovi60 Constraint surface

61. SVT INFN LNF - 28 Marzo 2007Alberto Annovi61 Online beamline fit & correction d phi d Subtracted Raw = Y beam cos  – X beam sin  Measure beam width as well --> input to Accelerator Division x y  d Transverse view

62. SVT INFN LNF - 28 Marzo 2007Alberto Annovi62 AM++

63. SVT INFN LNF - 28 Marzo 2007Alberto Annovi63 Pulsar in SVT++ Implement new boards with Pulsars: Fast enough to handle the new amount of data SVT interface built in Developers can concentrate on firmware (= board functionalities) The Pulsar board is a programmable board: 3 powerful FPGAs embedded RAM all CDF connectors modular mezzanines S-link I/O RAM extension Pulsar @ CDF --> FPGAs @ board devel. RAM mezzanine 4Mx48bits

64. SVT INFN LNF - 28 Marzo 2007Alberto Annovi64

65. SVT INFN LNF - 28 Marzo 2007Alberto Annovi65 ATLAS TDR 016

66. SVT INFN LNF - 28 Marzo 2007Alberto Annovi66 Why SVT succeeded –Performance: Parallel/pipelined architecture Custom VLSI pattern recognition Linear track fit in fast FPGAs –Reliability: Easy to sink/source test data (many boards can self-test) Modular design; universal, well-tested data link & fan-in/out Extensive on-crate monitoring during beam running Detailed CAD simulation before prototyping –Flexibility: System can operate with some (or all) inputs disabled Building-block design: can add/replace processing steps Modern FPGAs permit unforeseen algorithm changes –Key: design system for easy testing/commissioning

67. SVT INFN LNF - 28 Marzo 2007Alberto Annovi67 Sector segmentation Subdivide the (pixel) detector in many  sectors –Keep data volume limited in each sector Combine information from at least 3 layers out of 4 in each sector –Momentum resolution of ~ few (<10)% at 10 GeV/c –Granularity driven by the minimum measurable p T for triggering purposes, without loosing efficiency ~80  sectors at the innermost radius –  ~ 4.5° matches to a module of 2 cm width –Well covering the bending of a track of 5 GeV p T and above Larger  sectors with increasing radii –Match the sensors widths This plan match with AMchip features!!! 26 cm 34 cm 42 cm 50 cm F. Palla (LECC06 workshop)

68. SVT INFN LNF - 28 Marzo 2007Alberto Annovi68 Conceptual design AM EV0 AM EV1 AM EV40...... Layer 0: ~25 fibers bringing ~40 Hits/12 ns 1 Hit/10 ns From other layers From other layers From other layers Distribute hits into different sets of storage units depending on EVent # Parallel IN Serial OUT...... Parallel IN Serial OUT Parallel IN Serial OUT 1 FPGA From Detector F. Palla (LECC06 workshop)

69. SVT INFN LNF - 28 Marzo 2007Alberto Annovi69 Occupancy studies GEANT4 simulation of pixelized tracking layers –Simulated 3500 minimum bias using latest Pythia settings events and group into chunks of 100 events per bunch crossing and 250 t-tbar events –Use current CMS layout (material budget) but different sensors granularity Layer No. Radius (cm) Hit/module/bx a No. detectors in  Hits/sector/bxªData rate*/module (Gbps) Data rate*/sector (Gbps) No. data links † /layer 1 263.18243569 1100 2 348.7367814125 900 3 425.84449878 700 4 503.75234655 600 ª average number on minimum bias events, t-t will contribute on average<<1 hit/det *20 bits/hit † for a data link speed of 5 Gbps Current links in CMS TIB Silicon Strip: 2000 @ 26 cm - 2600 @ 34 cm F. Palla (LECC06 workshop)