Today’s Outline Dynamic RAM (DRAM) DRAM Cell – The Hydraulic Analogy DRAM Block Diagram Types of DRAM
DRAM ICs Provide high storage capacity at low cost, it dominates the high-capacity memory applications. E.g : Primary RAM in computers DRAM in many ways similar to SRAM except it must be periodically “refreshed”
DRAM Cell It consist of Capacitor C and Transistor T. Capacitor store electric charge Sufficient charge = logic 1 Insufficient charge = logic 0 Transistor T Act as a switch Switch open = the charge on capacitor remains fixed (stored) Switch closed = charge flow in and out, this allows the cell to be READ or WRITE
Hydraulic Analogy for DRAM Cell (b) Small tank full = storing logic 1 (c) Small tank empty = storing logic 0 In this state the valve is closed
Hydraulic Analogy for DRAM Cell (d) To write a logic 1: Pump will fill up big tank Valve open Water flows from big tank to small tank Once small tank is full, the valve is closed (e) To write a logic 0: Pump will empty big tank Valve open Water flows from small tank to big tank Once small tank is emptied (almost emptied), the valve is closed
Hydraulic Analogy for DRAM Cell Note : Once the water level in storage increase or decrease in the READ operation, the level left in storage will not showing the actual value of the storage anymore. This is called Destructive Read To store the original value, we must perform a restore operation to the storage (to return the small tank to its original level)
Hydraulic Analogy for DRAM Cell (f) Reading 1 from storage (small tank) Large tank at known intermediate level Valve opened IF Water flow from small tank to large tank Water increase slightly in large tank This slight increase depict READ value of logic 1 from storage (g) Reading 0 from storage (small tank) Large tank at known intermediate level Valve opened IF Water flow from large tank to small tank Water decrease slightly in large tank This slight decrease depict READ value of logic 0 from storage
Logic Model of DRAM Dynamic RAM cell circuit In actual, there is another consideration for dynamic RAM. The analogous leakage (due to the use of capacitors) Due to this leaks, a full storage tank will eventually drain to a point which an increase in the level of the large tank on a READ operation cannot be observed. To compensate, a refresh is needed.
The addressing is applied serially in two parts: Row address Column address In order to hold the row address throughout the READ or WRITE operation, it is stored in a register. Signal that control the loading of the registers are: RAS : Row Address Strobe CASS : Column Address Strobe R/W : Read / Write OE : Output Enable Note : the LOW signals activate Read, Write and Output enable. This is because when Write operation is activated, there should not be any Data output.
DRAM : Block Diagram The refresh counter and refresh controller is used to control the refresh rate for the DRAM. Typical refresh rate is between 16 to 64 milliseconds 2 types of refresh: Distributed refresh (more commonly used) Burst refresh
DRAM Types FPM DRAM (Fast Page Mode DRAM) EDO DRAM (Extended Data Output DRAM) SDRAM (Synchronous DRAM) DDR SDRAM (Double Data Rate SDRAM) RDRAM (Rambus® DRAM) ECC (Error Correcting Code)
Table 9.2 : Morris Mano, pg 422 Do your own reading on types of DRAM