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Final Design Review FSAE Instrumentation Ryan Gunn John Lee Dan Van Winkle Ali Yilmaz.

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Presentation on theme: "Final Design Review FSAE Instrumentation Ryan Gunn John Lee Dan Van Winkle Ali Yilmaz."— Presentation transcript:

1 Final Design Review FSAE Instrumentation Ryan Gunn John Lee Dan Van Winkle Ali Yilmaz

2 Formula SAE Intercollegiate competition New car every year Cars designed for non-professional auto cross racer Over 120 international teams

3 Operational Concept Real time data capture Post Processing Data analysis and reduction

4 Sensors Shock Position Sensors Steering Position Sensor Accelerometer Wheel Speed Sensors Oil Pressure Sensor Brake Pressure Sensor Thermal Sensors

5

6 Front Sensors

7 Rear Sensors

8 Wheel Speed Sensors Hall Effect Sensor Wheel Slip Speed

9 Shock Position Rotary Potentiometers Shock length Load on wheels

10 Pressure Transducers Oil Pressure Design has been questioned previously in competition Brake Pressure Driver’s use of brakes

11 Additional Sensors Engine Tach Measured directly from coil Square wave Accelerometer 3 axis acceleration Steering Position

12 Thermocouples Heat exchange efficiency of radiator

13 PCB Various power and signal conditioning circuits Needed to be ruggedized Needed to be documented Needed easy to use software

14 Pspice Schematics

15 Pspice AC Sweep (cont)

16 Engine Tachometer

17 Front PCB Layout

18 Front Annotated

19 Front PCB Installed

20 Rear PCB Layout

21 Rear Annotated

22 Rear PCB installed

23 Parts List PartDigikey #ManufacturerManufacturer #Qty Cost per unit Cost per part 0.1 μf BC1148TR-ND Vishay K104Z15Y5VE5TL2 2$0.07$ μf BC1079TR-ND Vishay K153K15X7RF5TL2 1$ μfBC1112TR-NDVishay K223K15X7RH5TL2 2$0.15$ μf BC1151TR-ND Vishay K105Z20Y5VE5TL2 3$0.18$ μf ND Vishay 199D106X9010B1V1E3 5$0.95$ μf 199D104X9035A2V1E3-ND Vishay 199D104X9035A2V1E3 10$0.21$ V regulator ND Texas Instrument UA78L02ACLP 1$ V regulator KA78L10AZTA-ND Fairchild KA78L10AZTA 4$0.10$ pin terminal ND Pheonix Contact $ pin OSTVN06A150-ND Pheonix Contact OSTVN06A150 12$0.71$ pin terminal ND Pheonix Contact $0.83$ K Resistor RC1/410KKR-ND Stackpole RC 1/4 10K 10% R 6$0.12$ Resistor RC1/4220JR-ND Stackpole RC 1/ % R 2$0.13$ Resistor RC1/4680KR-ND Stackpole RC 1/ % R 2$0.12$0.24 1k Reistor RC1/41KKR-ND Stackpole RC 1/4 1K 10% R 3$0.12$ K Resistor RC1/420KJR-ND Stackpole RC 1/4 20K 5% R 1$0.13 Amp AD8620AR-ND Analog Devices AD8620AR 1$15.51 Diode 1N5240BFSTR-ND Fairchild 1N5240BTR 1$0.08 Switch EG1889-ND E-Switch RR3130ABLKBLKFS 1$3.48

24 Software Requirements Debug existing software Improve functionality Write documentation

25 Software Improvements Boot file Switch Timestamp USB Storage No intermediate step

26 Software Improvements - Boot File The logging program will be loaded in the memory on startup No need to connect a computer to start logging Faster and easier use of the system

27 Software Improvements - Switch Added functionality to turn it on/off with a switch The switch will stop logging when the run is done It will start logging again with a new log file

28 Software Improvements - Timestamp Log files were named cRIO_Log.dat Added functionality to create a different filename for every run Filename includes date and time Easier to identify files No risk of overwriting old log files

29 Software Improvements – USB Storage Added functionality to store files on a USB drive Not limited to 128 MB on the cRIO Can support up to 4 GB Easier to transfer files to the computer

30 Software Improvements – No Intermediate Step Got rid of intermediate step in reading log files Used to have two programs One to convert binary files to measurement files One to read the measurement files Combined the two into one program Easier to read the log files

31 Data Flow

32

33 Data Flow (FPGA) “FPGA – Buffered DAQ with DMA.vi” Set up analog and digital channels for acquisition Read in data from input channels Store in AI data cluster data structure (Real Time) Store in DMA FIFO data structure (Logging)

34 Data Flow

35 Data Flow (cRIO) “RT – Logging & RT.vi” Open FPGA reference from previous step Real Time Read in AI data cluster data structure Split clusters into component signals Perform calculations on raw data from sensors Display data to the end user

36 Data Flow (cRIO) (cont’d)

37 Data Flow

38 Data Flow (cRIO) (cont’d) Logging: Calibration of channels stored on cRIO Calibrate channels .xml file Read in FIFO data structure .dat file

39 Data Flow (cRIO) (cont’d)

40 Data Flow

41 Data Flow (PC) “Windows – Read LVM file.vi” Option to convert binary data files to.lvm file Open.lvm file Split signals from.lvm file to component waveforms Perform calculations on raw waveforms from sensors Display data to the end user

42 Data Flow (PC) (cont’d)

43 Recommendations Digital signal processing Improve modularity Additional power source Code simplification for improvement of real-time data stream Post run statistic breakdown


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