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Nagarajan MAPLD2005/195 1 High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end Aerospace Applications N Venkateswaran * M Arvind.

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Presentation on theme: "Nagarajan MAPLD2005/195 1 High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end Aerospace Applications N Venkateswaran * M Arvind."— Presentation transcript:

1 Nagarajan MAPLD2005/195 1 High Performance Low Power Single Chip Reconfigurable Supercomputer for High-end Aerospace Applications N Venkateswaran * M Arvind § C Karthik § G Karthik § V Vishwanath § K Viswanath § * Director, WA ran R esearch F ounda T ion, Chennai, India. § Research Trainee, WA ran R esearch F ounda T ion, listed in alphabetical order.

2 Nagarajan MAPLD2005/195 2 High-end Aerospace applications Space Docking Space Maneuvering Space Medicine Remote Sensing and Satellite Imaging

3 Nagarajan MAPLD2005/195 3 MIP SCOC Heterogeneity of the node (Matrix, Vector, Graph & Scalar) Algorithm Level Functional Units (ALFUs) Algorithm Level Instruction Set Architecture (ALISA) Hardware Compilers (PCOS & SCOS) Heterogeneous characteristics adaptable across special purpose applications.

4 Nagarajan MAPLD2005/195 4 MIP SCOC – PCOS & SCOS

5 Nagarajan MAPLD2005/195 5 Proposed Re-Configurable MIP SCOC Basic blocks based Reconfigurable Tree Inter and Intra reconfigurable ALFUs Fault Tolerance – Massively Redundant ALFUs Dynamic Reconfiguration 1. Block Level 2. Intra Block Level

6 Nagarajan MAPLD2005/195 6 Re-Configuration in ALFUs

7 Nagarajan MAPLD2005/195 7 Control & Clock in MIP SCOC Control 1. Distributed – PCOS Controller, SCOS Controller, Segment and Basic Block Level 2. Synchronized Clock  Three levels of clock – COS Level, Segment Level and Block Level (500 MHz, 1500 MHz, 3 GHz)

8 Nagarajan MAPLD2005/195 8 Low Power Aspects Reduction in number of Instructions Localized Memory Reduction in number of memory accesses  Operand fetch  Intermediate Data

9 Nagarajan MAPLD2005/195 9 Low Power Aspects -continued Simulation Synthetic application design Different class of algorithms Computation and Communication complexity Machine Instruction generation ALU instructions (Disassembler) MIP instructions (MIP compiler)

10 Nagarajan MAPLD2005/ FixedLeast Addressing in the instructions Addressing Modes Elementary units Atomic HLFUsFunctional Units Relatively Complex SimpleInstruction Set Not LocalizedLocalizedMemory Access Decompiled No. of instructions of the Syn-app IA-32MIP

11 Nagarajan MAPLD2005/ References N Venkateswaran, Arrvindh Shriraman, and S. Niranjan Kumar. “Memory in processor supercomputer on a chip processor design and execution semantics for massive single chip performance.” Fifth Workshop on Massively Parallel Processing (WMPP), IPDPS, N.Venkateswaran and WARFT Research Trainees. “Simulation Model for predicting The Multi-Million Neuron Interconnectivity involving Dendrites-Axon-Soma- Synapse of the Brain Regions whose BOLD-fMRI is known and Evolution of a Neurophysiologically Inspired Supercomputing Architecture for Modeling the Respective Brain Regions.” Presentation at Max Planck Institute of Medical Research Workshop, “Data driven Modeling and Computational Neuroscience” (DMCN) 2005, Heidelberg, Germany. N. Venkateswaran, Aditya Krishnan, Niranjan Soundarajan, and Arrvindh shriraman. “Memory in processor : A novel design paradigm for supercomputing architectures.” ACM SigArch Computer Architecture News, June N.Venkateswaran, Arvind M, Karthik C, Karthik G, Vishwanath V and Viswanath K. “Memory Efficient Application Execution In MIP SCOC”. Submitted to MEDEA Workshop on MEmory performance: DEaling with Applications, systems and architecture, ( Under Review )


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