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UC Regents Spring 2014 © UCBCS 152 L12: Virtual Memory 2014-2-27 John Lazzaro (not a prof - “John” is always OK) CS 152 Computer Architecture and Engineering.

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Presentation on theme: "UC Regents Spring 2014 © UCBCS 152 L12: Virtual Memory 2014-2-27 John Lazzaro (not a prof - “John” is always OK) CS 152 Computer Architecture and Engineering."— Presentation transcript:

1 UC Regents Spring 2014 © UCBCS 152 L12: Virtual Memory John Lazzaro (not a prof - “John” is always OK) CS 152 Computer Architecture and Engineering www-inst.eecs.berkeley.edu/~cs152/ TA: Eric Love Lecture Virtual Memory Play:

2 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Today’s Lecture - Virtual Memory Virtual address spaces Page table layout TLB design optionsVirtual machinesExceptions and interrupts

3 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory The Limits of Physical Addressing CPU Memory A0-A31 D0-D31 “Physical addresses” of memory locations Data All programs share one address space: The physical address space No way to prevent a program from accessing any machine resource Machine language programs must be aware of the machine organization Where we are in CS

4 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Apple II: A physically addressed machine Apple ][ (1977) Steve Wozniak Steve Jobs CPU: 1000 ns DRAM: 400 ns

5 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB Apple II: A physically addressed machine Apple ][ (1977)

6 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory The Limits of Physical Addressing CPU Memory A0-A31 D0-D31 “Physical addresses” of memory locations Data All programs share one address space: The physical address space No way to prevent a program from accessing any machine resource Machine language programs must be aware of the machine organization Programming the Apple ][...

7 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Solution: Add a Layer of Indirection CPU Memory A0-A31 D0-D31 Data User programs run in an standardized virtual address space Address Translation hardware managed by the operating system (OS) maps virtual address to physical memory “Physical Addresses” Address Translation VirtualPhysical “Virtual Addresses” Hardware supports “modern” OS features: Protection, Translation, Sharing

8 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory MIPS R4000: Address Space Model Process A Address Error 2 GB Process B Address Error 2 GB Process A and B have independent address spaces ASID = 12ASID = 13 ASID = Address Space Identifier When Process A writes its address 9, it writes to a different physical memory location than Process B’s address 9 May only be accessed by kernel/supervisor To let Process A and B share memory, OS maps parts of ASID 12 and ASID 13 to the same physical memory locations. All address spaces use a standard memory map Still works (slowly!) if a process accesses more virtual memory than the machine has physical memory

9 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory MIPS R4000: Who’s Running on the CPU? System Control Registers User cannot write supervisor/kernel bits. Supervisor cannot write kernel bit. User cannot change address translation configuration Status (12): Indicates user, supervisor, or kernel mode EntryLo0 (2): 8-bit ASID field codes virtual address space ID. or run other privileged instructions...

10 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory MIPS Address Translation: How it works “Physical Addresses” CPU Memory A0-A31 D0-D31 Data TLB also contains ASID and kernel/supervisor bits for virtual address VirtualPhysical “Virtual Addresses” Translation Look-Aside Buffer (TLB) Translation Look-Aside Buffer (TLB) A small fully-associative cache of mappings from virtual to physical addresses Fast common case: Virtual address is in TLB, process has permission to read/write it. What is the table of mappings that it caches?

11 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Page tables code virtual address spaces A machine usually supports pages of a few sizes (MIPS R4000): Physical Memory Space A valid page table entry codes physical memory “frame” address for the page A virtual address space is divided into blocks of memory called pages frame A page table is indexed by a virtual address Page Table (One per ASID) OS manages the page table for each ASID

12 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory V=0 pages either reside on disk or have not yet been allocated. OS handles V=0 “Page fault” In this example, physical and virtual pages must be the same size! The TLB caches page table entries MIPS handles TLB misses in software (random replacement). Other machines use hardware. for ASID Physical frame address TLB Page Table virtual address pageoff 2 framepage 2 50 physical address pageoff TLB caches page table entries. frame

13 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Page tables may not fit in memory! A table for 4KB pages for a 32-bit address space has 1M entries Each process needs its own address space! P1 indexP2 indexPage Offset bit virtual address Top-level table wired in main memory Subset of 1024 second-level tables in main memory; rest are on disk or unallocated Two-level Page Tables

14 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory V=0 pages either reside on disk or have not yet been allocated. OS handles V=0 “Page fault” What if a page resides on disk? TLB Page Table virtual address pageoff 2 framepage 2 50 physical address pageoff TLB caches page table entries. Question: What to do when a TLB miss causes an access to a page table entry with V=0? for ASID Physical frame address

15 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory VM and Disk: Page replacement policy... Page Table 1 0 useddirty Set of all pages in Memory Tail pointer: Clear the used bit in the page table Head pointer Place pages on free list if used bit is still clear. Schedule pages with dirty bit set to be written to disk. Freelist Free Pages Dirty bit: page has been written. Used bit: set to 1 on any reference Architect’s role: support setting dirty and used bits On page fault: deallocate page table entry of a page on the free list.

16 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB TLB Design Concepts

17 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory MIPS R4000 TLB: A closer look... “Physical Addresses” CPU Memory System A0-A31 D0-D31 Data Translation Look-Aside Buffer (TLB) VirtualPhysical “Virtual Addresses” Physical space larger than virtual space! Checked against CPU ASID

18 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Can TLB and caching be overlapped? Index Byte Select Valid Cache Block Cache TagsCache Data Data out Virtual Page NumberPage Offset Translation Look-Aside Buffer (TLB) Virtual Physical = Hit Cache Tag This works, but... Q. What is the downside? A. Inflexibility. VPN size locked to cache tag size.

19 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Can we cache virtual addresses? “Physical Addresses” CPU Main Memory A0-A31 D0-D31 Only use TLB on a cache miss ! Translation Look-Aside Buffer (TLB) VirtualPhysical “Virtual Addresses” A. Synonym problem. If two address spaces share a physical frame, data may be in cache twice. Maintaining consistency is tricky. Cache Virtual D0-D31 Downside: A subtle problem. What is it? Solution: Anti-aliasing. See book, page B-38.

20 UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Virtual Memory Recap VM: Uniform memory models, protection, sharing. Operating systems manage the page table and (often) the TLB A TLB acts as a fast cache for recent address translations.

21 UC Regents Spring 2014 © UCBCS 152 L12: Virtual Memory Break Play:

22 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB Running Windows on a Mac Depends on the meaning of the word “run” edition...

23 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB Method #1: Boot Camp Basic Idea: New Macs use Intel CPU and support chips. So, set up boot ROM to let you choose Win or OS X. +++ Great compatibility. Just add device drivers. +++ No performance hit: full-speed, use all RAM, etc. --- Must reboot to change OS. --- Sharing files between OS partitions securely is tricky.

24 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB Method #2: Run WINE on OS X Basic Idea: Emulate the Windows API in software running under OS X. Lets you run Windows apps in a “compatibility box” without running Windows. +++ Do not need to buy Windows. +++ No reboot to run Win-app. --- Slow. --- Chances are, the app you want to run has compatibility woes.

25 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB Method 3: Virtual PC Basic Idea: Make a software emulation of PC hardware. Runs as a user process under OS X. Boot Windows and run apps on the emulator. +++ Runs on PowerPC Macs. +++ Good compatibility. Easier to emulate CPU than Win API. --- Must buy Windows. --- Slow

26 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB Emulating a PC --> emulating everything! Windows expects to see raw disks, so VirtualPC has Virtual Disks. Windows expects to manipulate page tables, so VirtualPC has Virtual TLB. Windows expects to to configure network: Virtual Ethernet Card. Windows expects to set up a graphics card, to VirtualPC has a Virtual GPU. Like the movie “The Truman Show”... no wonder its slow.

27 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB Method 4: Parallels, a Virtual Machine Basic Idea: Like emulating a PC, but different. Use an Intel-based Mac, runs on top of OS X. Uses hardware support to create a fast virtual PC that boots Windows. Source: +++ Reasonable performance. Virtual CPU runs 33% slower than running on physical CPU. 2 GB physical memory for a 512 MB virtual PC to run w/o disk swaps. (2006 data)

28 CS 152 L15: Virtual MemoryUC Regents Fall 2006 © UCB “Hardware assist?” What do we mean? In an emulator, we run Windows code by simulating the CPU in software. In a virtual machine, we let safe instructions (ex: ADD R3 R2 R1) run on the actual hardware in user mode. We use hardware features to prevent direct execution of unsafe instructions (ex: change a page table entry). We trap each attempt, and emulate the instruction in software, in a safe way. A “trap” is one type of “exception”...

29 UC Regents Fall 2008 © UCBCS L10: Advanced Processors II Exceptions and Interrupts Exception: An unusual event happens to an instruction during its execution. Examples: divide by zero, undefined opcode. Interrupt: Hardware signal to switch the processor to a new instruction stream. Example: a sound card interrupts when it needs more audio output samples (an audio “click” happens if it is left waiting).

30 UC Regents Fall 2008 © UCBCS L10: Advanced Processors II Challenge: Precise Interrupt / Exception Definition: Follows from the contract between the architect and the programmer... (or exception)

31 UC Regents Fall 2008 © UCBCS L10: Advanced Processors II Precise Exceptions in Static Pipelines Key observation: architected state only changes in memory and register write stages.

32 UC Regents Fall 2008 © UCBCS L10: Advanced Processors II Adding trap support to pipelines... decode, set an Exc E bit Call the code to be run on this trap type. Pass along Cause and EPC as arguments.

33 Virtual Machines: Better as servers than clients

34 Google runs Linux servers running the KVM module (Kernel Virtual Machine Monitor) and spins up VMs with varying specs on demand.

35 $2/hour for a 16-virtual-core 104GB machine...

36 Shell command for managing VMs... Command-line arguments set RAM, disk, network... and the OS to install. VMs can be monitored and reconfigured on the fly.

37 Under the hood What Google customers “think” is happening. (Guest) What actually happens. Where Google runs “make new VM” commands When the guest OS tries to privileged instructions, host kernel intercepts.

38 Example: Paging Guest OS runs instructions that manipulate page tables, and as far as it can tell everything works OK. Exists to “fake out” guest OS. Hypervisor watches every Guest OS move, and updates the “shadow” page tables and TLB to work correctly.

39 Hardware Support Intel VT-x adds a new level of privilege where hypervisors can run (VMX root). Guest OS’s run in “kernel mode” (ring 0) like they do on bare metal. Hypervisor relieved from faking guest privilege levels.

40 Hardware Support Intel VT-x supports Extended Page Tables (EPT). The TLB and the page replacement hardware tracks the shadow/guests page mappings.

41 A work in progress Each generation of Intel server adds new features for virtualization, and improves the latency for getting in and out of VMX root mode for critical operations.

42 On Tuesday Memory semantics for multi-core... Have a good weekend !


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