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ECE 4436ECE 5367 ISA II Microprocessor without Interlocked Piped Stages Million Instructions Per Second Meaningless indicator of Performance.

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Presentation on theme: "ECE 4436ECE 5367 ISA II Microprocessor without Interlocked Piped Stages Million Instructions Per Second Meaningless indicator of Performance."— Presentation transcript:

1 ECE 4436ECE 5367 ISA II Microprocessor without Interlocked Piped Stages Million Instructions Per Second Meaningless indicator of Performance

2 ECE 4436ECE 5367 Addressing Objects: Endianess and Alignment Big Endian: address of most significant byte = word address (xx00 = Big End of word) IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: address of least significant byte = word address (xx00 = Little End of word) Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msb lsb little endian byte big endian byte 0 Alignment: require that objects fall on address that is multiple of their size Aligned Not Aligned

3 ECE 4436ECE 5367 MIPS Assembly Language: Instruction Set 3 different instruction formats I-type, R-type,

4 ECE 4436ECE 5367 R-type instructions R-type Three register operands Arithmetic & logical opcodes Format: Rd = destination operand (output) Rs = source operand (input) Rt = source operand (input) 6 bits5 bits 6 bits OpcodeRsRtRdshamtfunction

5 ECE 4436ECE 5367 I-type instructions. I-type Two registers and an immediate Format: Rt = destination operand Rs = source operand Immediate = a constant, also a source operand Note: immediate operand must fit into 16 bits! (Why?) 6 bits5 bits 6 bits OpcodeRsRtaddress

6 ECE 4436ECE 5367 I-type instructions contd… I-type: 4 fields I-type at work ADDI$2,$1,32 LUI $7,OxABCD 6 bits5 bits 6 bits OpcodeRsRtaddress

7 ECE 4436ECE 5367 Flow control instructions

8 ECE 4436ECE 5367 Unconditional Branch

9 ECE 4436ECE 5367 Unconditional jump

10 ECE 4436ECE 5367 example

11 ECE 4436ECE 5367 Branch formats

12 ECE 4436ECE 5367 Unconditional Branch Jlabel transfer control unconditionally to instruction following label Ex. loop:add$t1,$s3,$s3 sw$t1,8($s4) jloop Why is the above code segment poor programming?

13 ECE 4436ECE 5367 Conditional Branches Ex 1: Ex 2: $s0==$s1? No Yes label23 c < 7? No Yes label17

14 ECE 4436ECE 5367 Conditional Branches Ex 3: if (i==j) f=f-i; else f=g+h;

15 ECE 4436ECE 5367 Branching far away…. 26 bit field in jump instructions is a word address It represents a word address Due to the fact that instructions are located at multiples of 4, the 2 LSbits are always 00 !!!!!! Implicit and can be dropped CPU appends the 2bits back on the instruction when instruction is fetched and decoded.

16 ECE 4436ECE 5367 For & While Loops Using Arrays Ex.clear an uninitialized array intarrayA[100]; for(i=0; i<100; i++) arrayA[i] = 0; Let i = $S3 base addr. of A = $S4 100 = $t1

17 ECE 4436ECE 5367 For & While Loops Using Arrays.data arrayA:.space 400….text LI$t1,100# load count MOVE$s3,$zero# i = 0 LA$s4,arrayA# load base addr. of A LOOP:BGE$s3,$t1,DONE# done? ADD$t2,$s3,$s3# i  2 * i ADD$t2,$t2,$t2# double again ADD$t2,$t2,$s4# ArrayA[i] SW$zero,0($t2)# ArrayA[i] ADDi$s3,$s3,1# i++ JLOOP DONE: Int: mult By 4

18 ECE 4436ECE 5367 Addressing Mode

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25 ECE 4436ECE 5367 Variable Declarations Memory is a linear array of bytes Used to store programs and data Memory is numbered in bytes MIPS can access up to 2 32 bytes i.e. from to FFFFFFFF 16 range of _______ to _______(??Bytes) Note: addresses are always unsigned

26 ECE 4436ECE 5367 Variable Declarations Every memory cell has two attributes address (location) contents Note: Recall registers are accessed by name Note: We may give a location a name for convenience 5F89025C B94 16 sum

27 ECE 4436ECE 5367 Variable Declarations In MIPS, two types of memory accesses are supported 1. Load Register with contents of a memory cell 2. Store Register into a memory cell Reg Memory Reg

28 ECE 4436ECE 5367 Variable Declarations In MIPS, 3 cell sizes can be accessed: bytelb halfword (2 bytes)sh word (4 bytes)lw All accesses must be aligned addresses of words must be divisible by 4 addresses of halfwords must be divisible by 2 bytes are always aligned

29 ECE 4436ECE 5367 Data Allocation In assembly language, we need to allocate memory for use by program assign names to memory locations (declare variables) initialize memory.data # start of data declarations

30 ECE 4436ECE 5367 Data Allocation To allocate uninitialized memory, use.space To allocate initialized memory, use.byte,.half,.word,.ascii,.asciiz To assign names to locations, prepend allocation directive with a label

31 ECE 4436ECE 5367 Data Allocation Examples. byte7# allocate byte and put a 7 in it.half15# allocate halfword and put a 15 in it.word9# allocate word and put a 9 in it

32 ECE 4436ECE 5367 Data Allocation Ex. (assume we start at address 0 after.data directive) a:.word0xab b:.word0x1234 c:.word 0x Symbol Table: a = b = c =

33 ECE 4436ECE 5367 Data Allocation Can also draw memory in words a: 0 b: 4 c: 8 a:.word0xab b:.word0x1234 c:.word0x

34 ECE 4436ECE 5367 Data Allocation Multiple numeric values separated by commas indicate repeat of directive Useful for small initialized arrays Ex.: a:.word1,2,3 b:.word4,5 a:.word1.word 2.word3 b:.word4.word5

35 ECE 4436ECE 5367 Data Allocation Memory Map a: 0 b: 12 a:word1,2,3 b:word4,5

36 ECE 4436ECE 5367 Data Allocation Ex..data datanums:.byte1,2,3,4 datanums: 0

37 ECE 4436ECE 5367 Alignment in MIPS Words are said to be aligned if they begin on a 4 byte boundary. Halfwords are said to be aligned if they begin on a 2 byte boundary Bytes are always aligned!

38 ECE 4436ECE 5367 Alignment in MIPS Default in MIPS is ALIGNED memory allocation i.e. .word means allocate at next quad address (divisible by 4) .half means allocate at next even address (divisible by 2) When you skip locations, they are uninitialized

39 ECE 4436ECE 5367 Alignment in MIPS Ex..data a:.word 1 b:.byte2 c:.half3 d:.byte4 e:.word0x Symbol 0 Location

40 ECE 4436ECE 5367 Alignment in MIPS Q: Why bother aligning data? A: Because the databus is 32 bits wide. (i.e. memory is accessed on word boundaries.) An unaligned access cannot be done in a single transfer sum

41 ECE 4436ECE 5367 Uninitialized Allocation:.space.spacen# allocate n bytes Ex..data a:.space4 b:.word4 c:.space4 d:.ascii“4” a: 0

42 ECE 4436ECE 5367 Allocating Memory for ASCII Strings Ex..data string1:.ascii“abcdef” string2:.asciiz“abcdef” number1:.word0x1234 string1: Symbol Table:

43 ECE 4436ECE 5367 Allocating Memory: C example Convert the C code to MIPS machine language int a,b=5,c[3]={7,8,9}; char string1 = “abcd”; char array1[10]; short int array2[7]; int d=0xAB.data a:.word 0 b:.word 5 c:.word 7.word 8.word 9 string1:.asciiz “abcd” array1:.space 10.space 1 array2:.space 14 d:.word 0xAB align manually auto align

44 ECE 4436ECE 5367 Allocating Memory: C example

45 ECE 4436ECE 5367 Allocating Memory: C example Symbol Table a b c string1 array1 array2 d

46 ECE 4436ECE 5367 Loading from Memory to Register Storing from Register to Memory To get stuff into and out of registers, must use load & store instructions Only way to access memory Memory access => Read or write from or to memory

47 ECE 4436ECE 5367 Loading from Memory to Register Storing from Register to Memory LoadsLxxRt, memory_address e.g.LW $S1,100($S2) Memory[$S2+100]  $S1 Load word from memory location to register StoresSxxRt, memory_address e.g.SB$S1,100($S2) $S1  Memory[$S2+100] Store byte from register to memory location

48 ECE 4436ECE 5367 Loading from Memory to Register Load  get contents of appropriate # of bytes from memory starting at address memadd and put into register Rt starting with low order.  if # of bytes < 4, then fill high order with 0’s or sign as indicated by instruction Note: loads always affect the entire register! (=> sign extension)

49 ECE 4436ECE 5367 Loading from Memory to Register List of load instructions LW load word (4 bytes) LH load half word (2bytes) -- fill high order with sign LHU load half word (2bytes) -- fill high order with 0’s LB load byte (1 byte) -- fill high order with sign LBU load byte (1 byte) -- fill high order with 0’s

50 ECE 4436ECE 5367 Storing from Register to Memory Store  List of store instructions SWstore word (4 bytes) SHstore half word (2bytes) SBstore byte (1 byte) Store appropriate # of bytes from Rt, (starting with low order) into memory starting at address memadd

51 ECE 4436ECE 5367 Sign Extension for Value Preservation Sign extension is required to preserve value when moving a 2’s complement number from a smaller cell to larger cell. Why? Given: 16 bit register (for simplicity) Want to store -7 in the register What is -7 in 4-bit 2’s complement binary? How do we store it in 16 bits?

52 ECE 4436ECE 5367 Sign Extension for Value Preservation Some examples: Ex. 1: -1 in 8 bits= -1 in 32 bits = Ex. 2: -7 in 8 bits = -7 in 32 bits =

53 ECE 4436ECE 5367 Sign Extension for Value Preservation Example 3: in 8 bits = in 32 bits =

54 ECE 4436ECE 5367 Sign Extension for Value Preservation When moving a 2’s complement # from an m- bit cell to an n-bit cell where n>m, the value is preserved if bits x n-1...x m are set to all 0’s if x is positive (x m-1 =0) all 1’s if x is negative (x m-1 =1) Another way to say: 2’s complement #’s preserve value when the sign is extended. (i.e. Copy bit x m-1 into x n-1...x m )

55 ECE 4436ECE 5367 Loading and Storing using Direct Mode Address known at load time (before execution) Ex:.data a:.wordOx1 b:.wordOxFFFFFFFF c:.halfOx7890 d:.halfOxABCD e:.byteOx10 f:.byteOxEE g:.word0 Addr.ValueAddr.Value 0D 1E 2F A17 B18 C19

56 ECE 4436ECE 5367 Loading and Storing using Direct Mode LW$t0,a SW$t0,g LH$t1,d LHU$t2,d LH$t3,c SB$t1,e LB$t4,f SW$t4,b

57 ECE 4436ECE 5367 Loading and Storing using Direct Mode Legal LB $t0,a SH $t0,e LW $t0,e (Not good programming) Illegal LW $t0,f SW $t0,d SH $t0,f Note: Assembly language does not care about declarations, only alignment

58 ECE 4436ECE 5367 Quick Review Part 1 Memory Allocation/Initialization.data a:.wordOx56 c:.halfOx7623 e:.byteOx10 g:.word0


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