1. Lecture 1 ECE 412: Microprocessor Laboratory Lecture 1: Course Introduction

2. Lecture 1 Outline Course Overview Administration Grading Equipment

3. Lecture 1 Course Outline Microprocessor Interfacing –Making processors talk to other devices CPUs not so interesting if you can’t get data in or out –Making hardware talk to software Key to the construction of systems that provide sophisticated functionalities and user interfaces Design –Designing systems is something of an art, but there are techniques we can teach –Tools and standards make more a discipline

4. Lecture 1 Lab: The Soul of the Course Three machine problems and one design project –MP1: VHDL, intro to the lab equipment –MP2: Connecting hardware to Linux –MP3: Video and the NTSC standard –MP4: Design your own system, a.k.a. “The Project” Teaming –MP1 is individual –Form teams for MP2 and MP3 –MP4 done as team, doesn’t have to be the same team as MP2, MP3 Lab space: EL 231 –Privileged access, ends by May 14, and does allow students to have access over spring break

5. Lecture 1 MP1 Introduction to Field Programmable Gate Arrays –This laboratory assignment serves as an introduction to the Xilinx Field Programmable Gate Array (FPGA) design systems. –You will become familiar with XUP board that will be used as the platform for all future ECE 412 machine problems. –You will use Precision Synthesis to compile and optimize a hardware description written in VHDL and the Xilinx ISE to map, place, route, and download to the FPGA.

6. Lecture 1 MP2 Introduction to Hardware/Software Co- Design –This laboratory assignment provides a more detailed and involved approach at VHDL design than MP1. –It also introduces the concept of SoC (system on a chip) systems. –You will become familiar with the Xilinx EDK software tool designed for hardware/software co- design. –You will also have an opportunity to write a device driver under Linux for a custom piece of hardware.

7. Lecture 1 MP3 Image Capture Hardware –This laboratory assignment serves as an introduction to image capture and display hardware. –You will become familiar with the video hardware available to you on the XUP-attached Digilent VDEC which may prove useful in your design project. –This lab will teach you how to capture image data from an NTSC source in YUV format, convert it to RGB, and display it on a VGA monitor.

8. Lecture 1 MP4 Open-ended Past projects –MP3 Player –XUP-GUI –Dance Dance Revolution –Network Storage –PAC-MAN –MPEG2 Enc/Dec –Network Packet Sniffing –Message Hiding –Duck Hunt –Night vision –…

9. Lecture 1 Course Goals Learn how to design systems that are buildable, verifiable, and maintainable –Abstraction –Interfaces –Testing Be skilled at common implementation techniques –VHDL, synthesis –Design to standards –Interrupts, memory-mapped I/O, device drivers –Building hardware and software that can interact

10. Lecture 1 People Professor: Deming Chen 410 CSL, [dchen@illinois.edu], 244-3922 Office hour: 5-6pm, Tuesday or through email. TA: Christine Chen, [chen150@illinois.edu], 333-7031 Office hours: decide now.

11. Lecture 1 Text/Notes O’Riley Linux Device Drivers Book –Free, available online at http://www.xml.com/ldd/chapter/book/index.html VHDL references Notes/Datasheet PCMCIA Manuals Most of above available in the course web site –http://courses.ece.uiuc.edu/ece412/ –ECE copyroom can make hard copies if desired

12. Lecture 1 Web Resources Web site: http://courses.ece.uiuc.edu/ece412http://courses.ece.uiuc.edu/ece412 –Copies of handouts –Lecture Slides –Documentation –Announcements: (although we will make the best effort, there is no guarantee that every announcement that is made in class will show up on the web.) Web board –Forum for electronic announcements –Also good place for questions and discussions Compass

13. Lecture 1 Grading Quizzes: 20% (10% each) Class Participation (5%) Labs: 75% –MP1: 10% –MP2: 15% –MP3: 15% –MP4: 35% Proposal/Initial Report: 20% Project Presentation: 20% Impact (usefulness, novelty, complexity): 30% Demo/Final Report: 30% MP1-MP3 Grading –Demo: 25% –Functionality: 40% –Report: 35%

14. Lecture 1 Bonus Days Each of you get six bonus days –A bonus day is a no-questions-asked one-day extension that can be used on most assignments –Bonus days are individual, but you can’t turn in multiple versions of a team assignment on different days, and you can’t trade them –You can use multiple bonus days on the same thing –Weekends/holidays don’t count for the number of days of extension (Friday-Monday is one day extension) Intended to cover illnesses, interview visits, just needing more time, etc. –Any requests for extensions beyond the bonus days should be for unusual circumstances, and will likely require some documentation.

15. Lecture 1 Using Bonus Days Web page has a bonus day form. Print it out, sign, and attach to the thing you’re turning in. Everyone who’s using a bonus day on an assignment needs to sign the form Penalty for being late beyond bonus days is 10% of the possible points/day, again counting only weekdays (spring break will count as weekdays) Things you can’t use bonus days on: –Quizzes –Final project design documents –Final project presentations –Final project demo (because they shut off access to the lab)

16. Lecture 1 Academic Honesty You are allowed and encouraged to discuss assignments with other students in the class. Getting verbal advice/help from people who’ve already taken the course is also fine. Any reference to assignments from previous terms is unacceptable Any copying of non-trivial code is unacceptable –Non-trivial = more than a line or so –Includes reading someone else’s code and then going off to write your own. –Doesn’t apply to members of your team on team MPs (duh) Giving/receiving help on a quiz is unacceptable Penalties for academic dishonesty: –Zero on the assignment for the first occasion –Automatic failure of the course for repeat offenses

17. Lecture 1 Team Projects Work can be divided up between team members in any way that works for you However, each team member will be required to demo the final checkpoint of each MP individually, and will get a separate demo grade –This will include questions about the entire design –Idea is that if you don’t know enough about the whole design to answer questions on it, you aren’t involved enough in the MP

18. Lecture 1 Lab Equipment Xilinx/Digilent XUP FPGA boards –Xilinx FPGA 2VP30 Approx. 30K logic cells plus 2 embedded PowerPC microprocessors More than 100 18-bit multipliers, 2Mb of block RAM Run Linux on the PowerPCs, communicate with hardware that you build –Video, audio in/out –Ethernet, USB, CF –Modules on IO connectors for SRAM, etc.

19. Lecture 1

20. Next lecture Design methodologies and FPGAs