Presentation on theme: "What is an “SoC”? SoC = SOC = System on Chip = System on a Chip Wider use: a Chip that implements a Complete System More common use: a Chip with one or."— Presentation transcript:
What is an “SoC”? SoC = SOC = System on Chip = System on a Chip Wider use: a Chip that implements a Complete System More common use: a Chip with one or more CPU cores, Peripheral Interface Blocks, and Dedicated HW Blocks around a System Bus
What is ASIC, FPGA, SoC? ASA AS ASIC ASA AS FPGA ASA AS SoC
Full-customASIC Gate-array (Structured ASIC) FPGA Layout Not Pre-designed Whole Chip Pre-designed Individual Gates and Memory Pre-designed All Layout except Wires Pre-designed SoC
From a Designer’s Perspective ASIC, FPGA, SoC: all the same from a designer’s point of view We are in the SoC age => Shop for IP blocks (IP block = Library block) Integrate them with each other and your design
What is ASIC? IC Full-custom IC IC = SP or ASSP SP = Standard Product = Memory chip, Processor ASSP = Application Specific Standard Product = USB interface chip for ex. ASIC => Think of Vestel or Cisco – an equipment=box=system maker that buys ICs (SP or ASSP) puts them on a PCB. They sometimes need extra logic => hence ASIC (Application Specific Integrated Circuit)
Contemporary (wider) meaning of ASIC Previous slide described the original (narrow) meaning of ASIC (how the word ASIC came about) Such chips required quick methods for design because: constraints in design time constraints in design personnel designs were not so aggressive This resulted in what we call: ASIC Design Flow Hence: an “ASIC Designer” doing “ASIC Design” may be working on an SP done in ASIC Design Flow as opposed to Full-Custom Flow.
Why/when design your own chip or customize an SoC? As opposed to taking a CPU and writing code that runs on it BECAUSE: CPU solution is not fast enough (FPGA is slower but offers more parallelism) CPU is too expensive CPU sucks too much power CPU cannot meet the exact I/O timing requirements (no later no earlier) CPU does not have the right number and mix of I/O pins Form-factor: CPU is too big and/or requires a heat/sink, fan, and/or chip-set
ASICFPGA NRENo NRE Lower unit cost in high volume Lower unit cost in low volume Faster Cheaper or free design tools Lower power Fast time to market Low barrier to entry Higher levels of integration More analog integration Programmable
- Next few slides are Courtesy of Xilinx (DAC 2001)
You hardly need anything you learned in your Logic course in Modern (HDL and Synthesis based) Digital Design because: We write code We don’t design circuits At least no gate-level circuits We don’t care about theorems in Boolean Algebra We don’t care about Karnaugh-maps The synthesis SW (compiler) does the logic minimization for us The FPGA has 1000s of gates anyway (OK, in some extreme cases we may need to care) Before we care about area minimization we need to care about meeting timing
What does RTL mean in the first place? RTL = RT-Level = Register Transfer Level
What is RT-Level digital (logic) design? Cloud of Logic (Combinational) Flop more Flops Inputs Outputs Your (RTL) code describes the logic cloud storedVars storedVars_next Everything is a STATE MACHINE!
Expressing ALGORITHMs in RT-Level paradigm? 1. Think of your HW module as a netlist of HW submodules. 2. Each submodule can in turn be a netlist of subsubmodules. 3. Leaf modules can be expressed by behavior that can be synthesized: (what we call) RTL code. 4. RTL is how we express an algorithm in HW. 5. Break your algorithm into clock cycles. 6.You have to specify what is done in each cycle.
Expressing ALGORITHMs in RT-Level paradigm? – cont’d 6. Think of it as a STATE MACHINE where every state is executed in a different cycle. 7. Store everything that needs top be remembered between states (= cycles) in explicitly coded REGISTERs. 8. Store also the STATE in an explicitly coded register. 9. At the top of the put a case(STATE). 10. What you will really code other than the registers is actually a Truth Table coded with a high-level language. 11. That is: Outputs depend on only inputs, which are external inputs plus register outputs.
GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*)
GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cntNxt) cntNxt = cnt –1; end cntNxt
GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cnt) cntNxt = cnt –1; end
GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cnt) cntNxt = cnt –1; else cntNxt = cntNxt; end
GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cnt) cntNxt = cnt –1; else cntNxt = cnt; end
GOLDEN RULE 1 – IMPLICATION Always have DEFAULT ASSIGNMENTS at the top of always @(*) always @(*) begin cntNxt = cnt; if(cnt) cntNxt = cnt –1; end
GOLDEN RULE 1 – IMPLICATION Always have DEFAULT ASSIGNMENTS at the top of always @(*) always @(*) begin cntNxt = cnt; if(cntNxt) cntNxt = cnt –1; end
GOLDEN RULE 2 NO INDIRECT COMBINATIONAL LOOPS always @(*) always @(*) and assign are equivalent
GOLDEN RULE 3 NO MULTIPLE DRIVERS always @(*) sameVar
GOLDEN RULE 3 NO MULTIPLE DRIVERS always @(*) begin cntNxt = cnt; if(btn1) cntNxt = cnt +1; end always @(*) begin cntNxt = cnt; if(btn2) cntNxt = cnt –1; end
GOLDEN RULE 3 NO MULTIPLE DRIVERS // Merge in a single always always @(*) begin cntNxt = cnt; if(btn1) cntNxt = cnt +1; if(btn2) cntNxt = cnt –1; end
Arbiter (~~~ Priority Encoder) GOLDEN RULE 3 NO MULTIPLE DRIVERS always @(*) var_v1 var_v2 always @(*) Extra input may be needed var
GOLDEN RULE 4 SINGLE CLOCK DOMAIN - unless really necessary - extra care needed for signals between different clock domains clk clk’ = derived clk = divided clk = gated clk in
GOLDEN RULE 4 Do NOT Write Anything in always @pos blocks other than flop definitions i.e. Flop <= #1 FlopNxt
GOLDEN RULE 5 SINGLE CLOCK DOMAIN - unless really necessary - extra care needed for signals between different clock domains 1 0 in clk
GOLDEN RULE 6 Do NOT Ignore Warning Messages other then the ones for #1’s.
GOLDEN RULE 7 Write a Testbench and Simulate! It is well worth the time.
HANDLING MULTIPLE CLOCKS Clocks with different frequencies Clocks with same frequency but different phases between them.
HANDLING MULTIPLE CLOCKS Setup Time and Hold Time violations Metastability Setup timeHold Time D Clock Stable 0Stable 1 Metastable state
HANDLING MULTIPLE CLOCKS Clock nomenclature Design partitioning One module should work on one clock only A synchronizer module be made for all signals that cross from one clock domain to another Sync 2 to1 Clock1 logic Sync 1to 2 Clock2 logic Clock1 domainClock2 domain Clk1_SigA Clk1_SigB Clk2_SigC Clk2_SigD
HANDLING MULTIPLE CLOCKS Transfer of Control Signals Src clock domain Dest clock domain src_ctrl dest_ctrl dest_clk Two-stage synchronizer
HANDLING MULTIPLE CLOCKS Transfer of DataSignals Handshake signaling method X clock domain Y clock domain data xreq xclk yclk
HANDLING MULTIPLE CLOCKS Transfer of DataSignals Asynchronous FIFO X clock domain Y clock domain Two-stage synchronizer xclk yclk FIFO write fifo_fullfifo_empty read