1. What is an “SoC”? SoC = SOC = System on Chip = System on a Chip Wider use: a Chip that implements a Complete System More common use: a Chip with one or more CPU cores, Peripheral Interface Blocks, and Dedicated HW Blocks around a System Bus

2. What is ASIC, FPGA, SoC? ASA AS ASIC ASA AS FPGA ASA AS SoC

3. Full-customASIC Gate-array (Structured ASIC) FPGA Layout Not Pre-designed Whole Chip Pre-designed Individual Gates and Memory Pre-designed All Layout except Wires Pre-designed SoC

4. Inside an FPGA CLB: Configurable Logic Block

5. An example of an ARM based MCU SoC

6. From a Designer’s Perspective ASIC, FPGA, SoC: all the same from a designer’s point of view We are in the SoC age => Shop for IP blocks (IP block = Library block) Integrate them with each other and your design

7. What is ASIC? IC Full-custom IC IC = SP or ASSP SP = Standard Product = Memory chip, Processor ASSP = Application Specific Standard Product = USB interface chip for ex. ASIC => Think of Vestel or Cisco – an equipment=box=system maker that buys ICs (SP or ASSP) puts them on a PCB. They sometimes need extra logic => hence ASIC (Application Specific Integrated Circuit)

8. Contemporary (wider) meaning of ASIC Previous slide described the original (narrow) meaning of ASIC (how the word ASIC came about) Such chips required quick methods for design because: constraints in design time constraints in design personnel designs were not so aggressive This resulted in what we call: ASIC Design Flow Hence: an “ASIC Designer” doing “ASIC Design” may be working on an SP done in ASIC Design Flow as opposed to Full-Custom Flow.

9. Why/when design your own chip or customize an SoC? As opposed to taking a CPU and writing code that runs on it BECAUSE: CPU solution is not fast enough (FPGA is slower but offers more parallelism) CPU is too expensive CPU sucks too much power CPU cannot meet the exact I/O timing requirements (no later no earlier) CPU does not have the right number and mix of I/O pins Form-factor: CPU is too big and/or requires a heat/sink, fan, and/or chip-set

10. a LOOK at the SECTOR

11. 1.Intel (USA): $50B 2.Samsung (Korea): $29B /$260B+ 3.TSMC (Taiwan):$15B 4.TI (USA): $14B 5.Toshiba (Japan): $13B /$80B 6.Renesas (Japan):$11B 7.Qualcomm (USA):$10B 8.STMicro (Fr-Ita): $10B 9.Hynix (Korea):$9B 10.Micron (USA):$7B 11.Broadcom (USA): $7B 12.AMD (USA):$6B 13.Infineon (Germany):$5B 14.Sony (Japan):$5B /$90B 15.Freescale (USA):$4B 16.Elpida (Japan):$4B 17.NXP (Holland):$4B 18.UMC (Taiwan):$4B 19.NVIDIA (USA):$4B 20.Globalfoundries (USA):$4B FPGA market size$5B Fab = Foundry Fabless semi Top Semi Companies (2011)

12. 1.Xilinx: 49% 2.Altera: 40% 3.Lattice:6% 4.Microsemi (was Actel): 4% 5.Quicklogic: 1% Top FPGA (=PLD=CPLD) Companies (all with HQs in the USA)

13. DESIGN ISSUES

14. ASIC Implementation Flow ASIC DesignFabricationPackage/TestValidation 3-12 months ~ 2 months ~ 1 month NRE = $100K - $4M SW tools = $100K - $1M

15. ASICFPGA NRENo NRE Lower unit cost in high volume Lower unit cost in low volume Faster Cheaper or free design tools Lower power Fast time to market Low barrier to entry Higher levels of integration More analog integration Programmable

16. - Next few slides are Courtesy of Xilinx (DAC 2001)

22. ASIC Design Flow Front-End DesignFront-End VerificationSpecification & Arch. Back-End Verification (Timing, GateSim, Formal, DRC, LVS) Back-End DesignSynthesis/Timing spec (behav. code) HDL RTL HDL gates Layout in GDSII

23. ASIC Design Tool-set Front-End DesignFront-End Verification Back-End Verification (Timing, GateSim, Formal, DRC, LVS) Back-End DesignSynthesis/Timing Layout in GDSII Editor Simulator SW HDL RTL HDL gates Synthesis SW Physical design, verif., DFT/ATPG SWs Stdcell Library

24. 1.Synopsys:$1500M 2.Mentor Graphics:$900M 3.Cadence:$850M 4.Other:27% (Above are my 2010 estimates. Total market size: $4.5B) Top EDA Companies (all with HQs in the USA)

25. FPGA Design Flow Front-End DesignFront-End VerificationSpecification & Arch. Back-End Verification (Timing, GateSim, Formal, DRC, LVS) Synthesis, Back-end, Timing spec (behav. code) Bitfile HDL RTL

26. FPGA Design Tool-set for Xilinx Front-End Design Front-End Verification Synthesis, Back-end, Timing Bitfile HDL RTL Xilinx ISE Editor, Simulator, Synthesis All in one IDE

27. MODERN DIGITAL DESIGN - BASICS -

28. You hardly need anything you learned in your Logic course in Modern (HDL and Synthesis based) Digital Design because: We write code We don’t design circuits At least no gate-level circuits We don’t care about theorems in Boolean Algebra We don’t care about Karnaugh-maps The synthesis SW (compiler) does the logic minimization for us The FPGA has 1000s of gates anyway (OK, in some extreme cases we may need to care) Before we care about area minimization we need to care about meeting timing

29. We write RTL code

30. What is RTL code?

31. What is the RTL programming paradigm?

32. What does RTL mean in the first place? RTL = RT-Level = Register Transfer Level

33. What is RT-Level digital (logic) design? Cloud of Logic (Combinational) Flop more Flops Inputs Outputs Your (RTL) code describes the logic cloud storedVars storedVars_next Everything is a STATE MACHINE!

34. for ex. INCREMENTER clk

35. INCREMENTER clk

36. INCREMENTER 0 0 0 0 0 0 0 1 clk time

37. INCREMENTER 0 0 0 1 0 0 0 1 clk time

38. INCREMENTER 0 0 0 1 0 0 1 0 clk time

39. INCREMENTER 0 0 1 0 0 0 1 0 clk time

40. INCREMENTER 0 0 1 0 0 0 1 1 clk time

41. INCREMENTER 0 0 1 1 0 0 1 1 clk time

42. INCREMENTER 0 0 1 1 0 1 0 0 clk time

43. Key points in this programming paradigm: What are we programming? How will we program? (Any guidelines?) What is a “flop” by the way?

44. Flop: What is it? Edge-Triggered D-Type Flip Flop = D-Type Flip Flop = Flip-Flop = Flop Edge-Triggered  Flip-Flop as opposed to: Level-Sensitive  Transparent Latch = Latch

45. Flop: explained with WAVEFORMS clk DQ D Q posedge Flop = 1-bit DigiCam

46. 2 Flops back to back = Shift Register clk D D Q1 Q2 Q1 Q2

47. How a FLOP behaves (shown with a SHIFT REGISTER) 10011 101 flop1flop2 t = before posedge clk

48. How a FLOP behaves (shown with a SHIFT REGISTER) 101 11001 flop1flop2 t = posedge clk

49. How a FLOP behaves (shown with a SHIFT REGISTER) 110 11100 flop1flop2 t = posedge clk + C2Q delay C2Q delay like good cholestrol

50. SWITCH = LATCH Latch = Transparent Latch DQ clk clk (= enable)

51. SWITCH = LATCH Latch = Transparent Latch DQ clk (= enable) clk

52. SWITCH = LATCH Latch = Transparent Latch D Q clk (= enable) 1 0

53. FLOP = 2 back-to-back LATCHes flop latch (master)latch (slave) clk clk1 clk2 clk clk1 clk2 ClockToQ (C2Q) delay C2Q delay NON-OVERLAPPING

54. Key points in this programming paradigm: What are we programming? Your program DESCRIBES this clk

55. Key points in this programming paradigm: What are we programming? Your program DESCRIBES ONE CYCLE clk

56. Key points in this programming paradigm: How will we program? Any guidelines? That brings us to…

57. VERILOG TUTORIAL - BASICS -

58. example design: counter counter module counter(); endmodule

59. example design: counter counter module counter( cnt ); output [3:0] cnt; endmodule 4 cnt

60. example design: counter counter module counter( cnt, btn ); output [3:0] cnt; input btn; endmodule 1 btn 4 cnt

61. example design: counter counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; endmodule 1 btn 4 cnt clk

62. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; endmodule 1 btn 4 cnt clk 4 cntNxt always @(*)

63. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; always @(posedge clk) begin cnt <= #1 cntNxt; end endmodule 1 btn 4 cnt clk 4 cntNxt

64. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; always @(posedge clk) begin cnt <= #1 cntNxt; end always @(*) begin if(btn) cntNxt = cnt +1; end endmodule 1 btn 4 cnt clk 4 cntNxt always @(*)

65. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; always @(posedge clk) begin cnt <= #1 cntNxt; end always @(*) begin if(btn) cntNxt = cnt +1; end endmodule btn 4 cnt clk 4 +1 1 0

66. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; always @(posedge clk) begin cnt <= #1 cntNxt; end always @(*) begin cntNxt = cnt; if(btn) cntNxt = cnt +1; end endmodule btn 4 cnt clk 4 +1 1 0

67. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; reg prevBtn, posedgeBtn; always @(posedge clk) begin cnt <= #1 cntNxt; prevBtn <= #1 btn; end always @(*) begin cntNxt = cnt; posedgeBtn = ~prevBtn & btn; if(posedgeBtn) cntNxt = cnt +1; end endmodule btn cnt prevBtn

68. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; reg prevBtn; always @(posedge clk) begin cnt <= #1 cntNxt; prevBtn <= #1 btn; end always @(*) begin cntNxt = cnt; if(~prevBtn & btn) cntNxt = cnt +1; end endmodule btn cnt prevBtn

69. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; reg prevBtn; wire posedgeBtn; always @(posedge clk) begin cnt <= #1 cntNxt; prevBtn <= #1 btn; end assign posedgeBtn = ~prevBtn & btn; always @(*) begin cntNxt = cnt; if(posedgeBtn) cntNxt = cnt +1; end endmodule btn cnt prevBtn assign always @(*)

70. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; reg prevBtn; wire posedgeBtn; always @(posedge clk) begin cnt <= #1 cntNxt; end posDet posDet(clk, btn, posedgeBtn); always @(*) begin cntNxt = cnt; if(posedgeBtn) cntNxt = cnt +1; end endmodule btn cnt posDet clk

71. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; reg prevBtn; wire posedgeBtn; always @(posedge clk) begin cnt <= #1 cntNxt; prevBtn <= #1 btn; end assign posedgeBtn = ~prevBtn & btn; always @(*) begin cntNxt = cnt; if(posedgeBtn) cntNxt = cnt +1; end endmodule btn cnt prevBtn assign always @(*)

72. example design: counter btn cnt prevBtn assign always @(*) module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; reg prevBtn; wire posedgeBtn; always @(posedge clk) begin cnt <= #1 cntNxt; prevBtn <= #1 btn; end always @(*) posedgeBtn = ~prevBtn & btn; always @(*) begin cntNxt = cnt; if(posedgeBtn) cntNxt = cnt +1; end endmodule

73. example design: counter module counter(cnt, btn, clk); output [3:0] cnt; input btn, clk; reg [3:0] cnt, cntNxt; reg prevBtn, posedgeBtn; always @(posedge clk) begin cnt <= #1 cntNxt; prevBtn <= #1 btn; end always @(*) begin cntNxt = cnt; posedgeBtn = ~prevBtn & btn; if(posedgeBtn) cntNxt = cnt +1; end endmodule btn cnt prevBtn

74. Expressing ALGORITHMs in RT-Level paradigm? 1. Think of your HW module as a netlist of HW submodules. 2. Each submodule can in turn be a netlist of subsubmodules. 3. Leaf modules can be expressed by behavior that can be synthesized: (what we call) RTL code. 4. RTL is how we express an algorithm in HW. 5. Break your algorithm into clock cycles. 6.You have to specify what is done in each cycle.

75. Expressing ALGORITHMs in RT-Level paradigm? – cont’d 6. Think of it as a STATE MACHINE where every state is executed in a different cycle. 7. Store everything that needs top be remembered between states (= cycles) in explicitly coded REGISTERs. 8. Store also the STATE in an explicitly coded register. 9. At the top of the put a case(STATE). 10. What you will really code other than the registers is actually a Truth Table coded with a high-level language. 11. That is: Outputs depend on only inputs, which are external inputs plus register outputs.

76. GOLDEN RULES L

77. GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*)

78. GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cntNxt) cntNxt = cnt –1; end cntNxt

79. GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cnt) cntNxt = cnt –1; end

80. GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cnt) cntNxt = cnt –1; else cntNxt = cntNxt; end

81. GOLDEN RULE 1 NO COMBINATIONAL LOOP always @(*) always @(*) begin if(cnt) cntNxt = cnt –1; else cntNxt = cnt; end

82. GOLDEN RULE 1 – IMPLICATION Always have DEFAULT ASSIGNMENTS at the top of always @(*) always @(*) begin cntNxt = cnt; if(cnt) cntNxt = cnt –1; end

83. GOLDEN RULE 1 – IMPLICATION Always have DEFAULT ASSIGNMENTS at the top of always @(*) always @(*) begin cntNxt = cnt; if(cntNxt) cntNxt = cnt –1; end

84. GOLDEN RULE 2 NO INDIRECT COMBINATIONAL LOOPS always @(*) always @(*) and assign are equivalent

85. GOLDEN RULE 3 NO MULTIPLE DRIVERS always @(*) sameVar

86. GOLDEN RULE 3 NO MULTIPLE DRIVERS always @(*) begin cntNxt = cnt; if(btn1) cntNxt = cnt +1; end always @(*) begin cntNxt = cnt; if(btn2) cntNxt = cnt –1; end

87. GOLDEN RULE 3 NO MULTIPLE DRIVERS // Merge in a single always always @(*) begin cntNxt = cnt; if(btn1) cntNxt = cnt +1; if(btn2) cntNxt = cnt –1; end

88. Arbiter (~~~ Priority Encoder) GOLDEN RULE 3 NO MULTIPLE DRIVERS always @(*) var_v1 var_v2 always @(*) Extra input may be needed var

89. GOLDEN RULE 4 SINGLE CLOCK DOMAIN - unless really necessary - extra care needed for signals between different clock domains clk clk’ = derived clk = divided clk = gated clk in

90. GOLDEN RULE 4 Do NOT Write Anything in always @pos blocks other than flop definitions i.e. Flop <= #1 FlopNxt

91. GOLDEN RULE 5 SINGLE CLOCK DOMAIN - unless really necessary - extra care needed for signals between different clock domains 1 0 in clk

92. GOLDEN RULE 6 Do NOT Ignore Warning Messages other then the ones for #1’s.

93. GOLDEN RULE 7 Write a Testbench and Simulate! It is well worth the time.

94. HANDLING MULTIPLE CLOCKS Clocks with different frequencies Clocks with same frequency but different phases between them.

95. HANDLING MULTIPLE CLOCKS Setup Time and Hold Time violations Metastability Setup timeHold Time D Clock Stable 0Stable 1 Metastable state

96. HANDLING MULTIPLE CLOCKS Clock nomenclature Design partitioning One module should work on one clock only A synchronizer module be made for all signals that cross from one clock domain to another Sync 2 to1 Clock1 logic Sync 1to 2 Clock2 logic Clock1 domainClock2 domain Clk1_SigA Clk1_SigB Clk2_SigC Clk2_SigD

97. HANDLING MULTIPLE CLOCKS Transfer of Control Signals Src clock domain Dest clock domain src_ctrl dest_ctrl dest_clk Two-stage synchronizer

98. HANDLING MULTIPLE CLOCKS Transfer of DataSignals Handshake signaling method X clock domain Y clock domain data xreq xclk yclk

99. HANDLING MULTIPLE CLOCKS Transfer of DataSignals Asynchronous FIFO X clock domain Y clock domain Two-stage synchronizer xclk yclk FIFO write fifo_fullfifo_empty read