Presentation is loading. Please wait.

Presentation is loading. Please wait.

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22,

Published byJaycee Stocke Modified over 9 years ago

Similar presentations

Presentation on theme: "10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22,"— Presentation transcript:

1 http://vsp2.ecs.umass.edu/vspg/vspg.html http://lester.univ-ubs.fr/ 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Targeting Tiled Architectures in Design Exploration Lilian Bossuet 1, Wayne Burleson 2, Guy Gogniat 1, Vikas Anand 2, Andrew Laffely 2, Jean-Luc Philippe 1 1 LESTER Lab Université de Bretagne Sud Lorient, France {lilian.bossuet, guy.gogniat, jean-luc.philippe}@univ-ubs.fr 2 Department of Electrical and Computer Engineering University of Massachusetts, Amherst, USA {burleson, vanand, alaffely}@ecs.umass.edu

2 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Space Exploration u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

3 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space Exploration: Motivations u Design solutions for new telecommunication and multimedia applications targeting embedded systems u Optimization and reduction of SoC power consumption u Increase computing performance è Increase parallelism è Increase speed u Be flexible è Take into account run-time reconfiguration è Targeting multi-granularity (heterogeneous) architectures

4 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space Exploration: Flow u Progressive design space reduction: è iterative exploration è refinement of architecture model  increase of performance estimation accuracy u One level of abstraction for one level of estimation accuracy

5 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Works

6 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Reconfigurable Architectures u Bridging the flexibility gap between ASICs and microprocessor [Hartenstein DATE 2001] u Energy efficient and solution to low power programmable DSP [Rabaey ICASSP 1997, FPL 2000] u Run Time Reconfigurable [Compton & Hauck 1999] u => A key ingredient for future silicon platforms [Schaumont & all. DAC 2001]

7 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space of Reconfigurable Architecture RECONFIGURABLE ARCHITECTURES (R-SOC) FINE GRAIN (FPGA) MULTI GRANULARITY (Heterogeneous) COARSE GRAIN (Systolic) Processor + Coprocessor Tile-Based Architecture Coarse Grain Coprocessor Fine Grain Coprocessor Island Topology Hierarchical Topology Linear Topology Hierarchical Topology Mesh Topology Chameleon REMARC Morphosys Pleiades Garp FIPSOC Triscend E5 Triscend A7 Xilinx Virtex-II Pro Altera Excalibur Atmel FPSIC Xilinx Virtex Xilinx Spartran Atmel AT40K Lattice ispXPGA Altera Stratix Altera Apex Altera Cyclone Systolic Ring RaPiD PipeRench DART FPFA RAW CHESS MATRIX KressArray Systolix Pulsedsp aSoC E-FPFA

8 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Works

9 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 A Target Architecture: aSoC u Adaptive System-on-a-Chip (aSoC) u Tiled architecture containing many heterogeneous processing cores (RISC, DSP, FPGA, Motion Estimation, Viterbi Decoder) u Mesh communication network controlled with statically determined communication schedule u A scalable architecture.

10 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 tile FPGA uProc MUL u Heterogeneous Cores aSoC Architecture u Point-to-point connections ctrl SouthCore West North East u Communication Interface

11 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Communications Interface Core Coreports Decoder Local Frequency & Voltage North to South & East Instruction Memory PC Controller North South East West LocalConfig. North South East West Inputs Outputs u Interface Crossbar è inter-tile transfer è tile to core transfer u Interconnect/Instruction Memory è contains instructions to configure the interface crossbar (cycle-by- cycle) u Interface Controller è selects the instruction u Coreports è data interface and storage for transfers with the tile IP core u Dynamic Voltage and Frequency Selection è Dynamic Power Management Interface Crossbar

12 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Exploration... u Type of tiles u Number of each type of tile u Placement of the tiles u Intern architecture of reconfigurable tiles (FPGA core) u Communication scheduling

13 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

14 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space Exploration: Goals u Goal: Rapid exploration of various architectural solutions to be implemented on heterogeneous reconfigurable architectures (aSoC) in order to select the most efficient architecture for one or several applications u Take place before architectural synthesis (algorithmic specification with high level abstraction language) u Estimations are based on a functional architecture model (generic, technology-independent) u Iterative exploration flow to progressively refine the architecture definition, from a coarse model to a dedicated model

15 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Exploration Flow Targeting Tiled Architecture

16 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Application Analysis u Use of algorithmic metrics and dedicated scheduling algorithms to highlight the target architectures u Algorithmic metrics: è Characterize the application orientation Processing Memory Control è Characterize the application potential parallelism Processing Memory

17 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Tile Exploration: with 3 steps u Projection: è Link between necessary resources (application) and available resources (tile) è Use of an allocation algorithm based on communication costs reduction u Composition: è Take into account of the function scheduling to estimate additional resources (register, mux, …) u Estimation: è performance interval computation (lower and upper bounds) è speed/resource utilization/power characterization

18 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Builder u Environment AppMapper u Partition and assignment è based on Run Time Estimation u Compilation è Communication Scheduling è Core compilation u Generate tiles configuration è Communications instructions è Bitstreams (for reconfigurable tile) è RISC instructions

19 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Analysis u Use the results of previous steps è Functions scheduling è Tile allocation è Communication scheduling u Complete estimation of the proposed solution è Global execution time è Global power consumption è Total area

20 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

21 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Results u aSoC architecture (UMASS) è Prototype of aSoC interconnect Technology 0.18 µm Clock speed of 400 MHz u AppMapper (UMASS) è Several mapped applications Matrix operations Median Filter Viterbi decoder DCT u Tile exploration (UBS) è Application analysis Intelligent Camera (motion detection) Matching Pursuit è Projection step Lee DCT Matrix operations

22 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

23 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Conclusion and future work u Conclusion è Original design exploration flow working at a high level of abstraction è Fast and flexible (use of functional view of the architectures) è Targeting an efficient reconfigurable architecture: aSoC è Statically-scheduled, point-to-point communications u Future Work è Development of larger set of design exploration benchmarks è Exploration of other configurable systems

24 http://vsp2.ecs.umass.edu/vspg/vspg.html http://lester.univ-ubs.fr/ 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Thank you...

25 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Previous Work u Xplorer - University of Kaiserslautern, Germany [Hartenstein PATMOS 2000] è Targets a mesh coarse grain architecture: The KressArray a fast reconfigurable ALUs è Gives design guidance concerning: the size of the array, the available operators, the communication architecture and the connection structure. è Controlled by performance and power estimations. è Starts with high level specification of application (ALE-X language). u RAW - Massachusetts Institute of Technology, USA [Moritz FCCM 1998] è Targets a reminiscent coarse grained FPGA: The MIT Raw Microprocessor è Answers to the balance problem: to determine the best division of VLSI resources among computing, memory and communication. è Answers to the grain problem: to determine the optimum size of each architecture tiles è Use several models: architecture model, costs model and performance model

26 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 HCDFG: Hierarchical Control Data Flow Graph Task 1Task 2 Task 1 F2 F1 F5 F4 F3 HCDFG HDFG LOOP DFG CDFG DFG Loop CORE X Y# C Y MAC ALU A

27 http://lester.univ-ubs.fr/ http://vsp2.ecs.umass.edu/vspg/vspg.html 10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Application’s Metrics Average Parallelism metric (a lot of parallelism if γ is high) Nb of global memory accesses and processing operations Critical Path γ = Nb of global memory accesses Nb of processing operations + Nb of global memory accesses MOM = Memory Orientation Metric [0,1] Nb of test Nb of global mem. accesses + Nb of proc. op. + Nb of test COM = Control Orientation Metric [0,1] Y. Le Moullec, N. Ben Amor, J-Ph. Diguet, M. Abid and J-L. Philippe. Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. In DATE 2002, Munich, Germany, March 2002

Download ppt "10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22,"

Similar presentations

Multiprocessor Architecture for Image processing Mayank Kumar – 2006EE10331 Pushpendre Rastogi – 2006EE50412 Under the guidance of Dr.Anshul Kumar.

Multiprocessor Architecture for Image processing Mayank Kumar – 2006EE10331 Pushpendre Rastogi – 2006EE50412 Under the guidance of Dr.Anshul Kumar.
System-level Architectur Modeling for Power Aware Computing Dexin Li.

System-level Architectur Modeling for Power Aware Computing Dexin Li.
© 2004 Wayne Wolf Topics Task-level partitioning. Hardware/software partitioning.  Bus-based systems.

© 2004 Wayne Wolf Topics Task-level partitioning. Hardware/software partitioning.  Bus-based systems.
LAB-STICC CNRS UMR 3192 – UBS – ROMAIN VASLIN – CRYPTARCHI 2008 Memory Security Management for FPGA-based Embedded system Romain Vaslin, Guy Gogniat, Jean-Philippe.

LAB-STICC CNRS UMR 3192 – UBS – ROMAIN VASLIN – CRYPTARCHI 2008 Memory Security Management for FPGA-based Embedded system Romain Vaslin, Guy Gogniat, Jean-Philippe.
The Microprocessor is no more General Purpose. Design Gap.

The Microprocessor is no more General Purpose. Design Gap.
A Survey of Logic Block Architectures For Digital Signal Processing Applications.

A Survey of Logic Block Architectures For Digital Signal Processing Applications.
Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.

Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.
5th International Conference, HiPEAC 2010 MEMORY-AWARE APPLICATION MAPPING ON COARSE-GRAINED RECONFIGURABLE ARRAYS Yongjoo Kim, Jongeun Lee *, Aviral Shrivastava.

5th International Conference, HiPEAC 2010 MEMORY-AWARE APPLICATION MAPPING ON COARSE-GRAINED RECONFIGURABLE ARRAYS Yongjoo Kim, Jongeun Lee *, Aviral Shrivastava.
FPGA Latency Optimization Using System-level Transformations and DFG Restructuring Daniel Gomez-Prado, Maciej Ciesielski, and Russell Tessier Department.

FPGA Latency Optimization Using System-level Transformations and DFG Restructuring Daniel Gomez-Prado, Maciej Ciesielski, and Russell Tessier Department.
Embedded Software Optimization for MP3 Decoder Implemented on RISC Core Yingbiao Yao, Qingdong Yao, Peng Liu, Zhibin Xiao Zhejiang University Information.

Embedded Software Optimization for MP3 Decoder Implemented on RISC Core Yingbiao Yao, Qingdong Yao, Peng Liu, Zhibin Xiao Zhejiang University Information.
Zheming CSCE715.  A wireless sensor network (WSN) ◦ Spatially distributed sensors to monitor physical or environmental conditions, and to cooperatively.

Zheming CSCE715.  A wireless sensor network (WSN) ◦ Spatially distributed sensors to monitor physical or environmental conditions, and to cooperatively.
Preventing Piracy and Reverse Engineering of SRAM FPGAs Bitstream Lilian Bossuet 1,

Preventing Piracy and Reverse Engineering of SRAM FPGAs Bitstream Lilian Bossuet 1,
Lecture 26: Reconfigurable Computing May 11, 2004 ECE 669 Parallel Computer Architecture Reconfigurable Computing.

Lecture 26: Reconfigurable Computing May 11, 2004 ECE 669 Parallel Computer Architecture Reconfigurable Computing.
Department of Electrical and Computer Engineering Configurable computing for high-security/high-performance ambient systems 1 Guy Gogniat, Lilian Bossuet,

Department of Electrical and Computer Engineering Configurable computing for high-security/high-performance ambient systems 1 Guy Gogniat, Lilian Bossuet,
Data Partitioning for Reconfigurable Architectures with Distributed Block RAM Wenrui Gong Gang Wang Ryan Kastner Department of Electrical and Computer.

Data Partitioning for Reconfigurable Architectures with Distributed Block RAM Wenrui Gong Gang Wang Ryan Kastner Department of Electrical and Computer.
Storage Assignment during High-level Synthesis for Configurable Architectures Wenrui Gong Gang Wang Ryan Kastner Department of Electrical and Computer.

Storage Assignment during High-level Synthesis for Configurable Architectures Wenrui Gong Gang Wang Ryan Kastner Department of Electrical and Computer.
Adaptive System on a Chip (aSoC) for Low-Power Signal Processing Andrew Laffely, Jian Liang, Prashant Jain, Ning Weng, Wayne Burleson, Russell Tessier.

Adaptive System on a Chip (aSoC) for Low-Power Signal Processing Andrew Laffely, Jian Liang, Prashant Jain, Ning Weng, Wayne Burleson, Russell Tessier.
UCB November 8, 2001 Krishna V Palem Proceler Inc. Customization Using Variable Instruction Sets Krishna V Palem CTO Proceler Inc.

UCB November 8, 2001 Krishna V Palem Proceler Inc. Customization Using Variable Instruction Sets Krishna V Palem CTO Proceler Inc.
HW/SW Co-Synthesis of Dynamically Reconfigurable Embedded Systems HW/SW Partitioning and Scheduling Algorithms.

HW/SW Co-Synthesis of Dynamically Reconfigurable Embedded Systems HW/SW Partitioning and Scheduling Algorithms.
1 Embedded Computer System Laboratory RTOS Modeling in Electronic System Level Design.

1 Embedded Computer System Laboratory RTOS Modeling in Electronic System Level Design.

Similar presentations

Ads by Google