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1 COMP541 Datapath & Single-Cycle MIPS Montek Singh Oct 27, 2014.

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1 1 COMP541 Datapath & Single-Cycle MIPS Montek Singh Oct 27, 2014

2 Topics  Complete the datapath  Add control to it  Create a full single-cycle MIPS!  Reading Chapter 7 Chapter 7 Review MIPS assembly language Review MIPS assembly language  Chapter 6 of course textbook  Or, Patterson Hennessy (inside front flap)

3 A MIPS CPU 3 MIPS CPU Instr Memory Data Memory pc instr memwrite dataadr readdata writedata clk reset

4 Top-Level: MIPS CPU + memories 4 MIPS CPU Instr Memory Data Memory pc instr memwrite dataadr readdata writedata clk reset clkreset We will add I/O devices (display, keyboard, etc.) later Top-level module

5 Top-Level MIPS: Verilog module top(input clk, reset, output … ); // add signals here for debugging output … ); // add signals here for debugging // we will add I/O later // we will add I/O later wire [31:0] pc, instr, readdata, writedata, dataadr; wire [31:0] pc, instr, readdata, writedata, dataadr; wire memwrite; wire memwrite; mips mips(clk, reset, pc, instr, memwrite, dataadr, mips mips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata);// processor writedata, readdata);// processor imem imem(pc[31:0], instr);// instr memory imem imem(pc[31:0], instr);// instr memory // send full PC to imem dmem dmem(clk, memwrite, dataadr, writedata, dmem dmem(clk, memwrite, dataadr, writedata, readdata);// data memory readdata);// data memoryendmodule

6 One level down: Inside MIPS  Datapath: components that store or process data  registers, ALU, multiplexors, sign-extension, etc.  we will regard memories as outside the CPU, so not part of the core datapath  Control: components that tell datapath what to do and when  control logic (FSMs or combinational look-up tables) MIPS CPU Control ALUFN, regwrite, regdst… opcode, func, flagZ … MIPS Datapath Instr Memory Data Memory pc instr memwrite dataadr readdata writedata clk reset clk

7 One level down: Inside MIPS module mips(input clk, reset, output [31:0] pc, output [31:0] pc, input [31:0] instr, input [31:0] instr, output memwrite, output memwrite, output [31:0] dataaddr, writedata, output [31:0] dataaddr, writedata, input [31:0] readdata); input [31:0] readdata); wire memtoreg, branch, pcsrc, wire memtoreg, branch, pcsrc, alusrc, regdst, regwrite, jump; alusrc, regdst, regwrite, jump; wire [4:0] ALUFN; wire [4:0] ALUFN; wire flagZ; wire flagZ; controller c(instr[31:26], instr[5:0], flagZ, controller c(instr[31:26], instr[5:0], flagZ, memtoreg, memwrite, pcsrc, memtoreg, memwrite, pcsrc, alusrc, regdst, regwrite, jump, alusrc, regdst, regwrite, jump, ALUFN); ALUFN); datapath dp(clk, reset, memtoreg, pcsrc, datapath dp(clk, reset, memtoreg, pcsrc, alusrc, regdst, regwrite, jump, alusrc, regdst, regwrite, jump, ALUFN, flagZ, pc, instr, ALUFN, flagZ, pc, instr, dataddr, writedata, readdata); dataddr, writedata, readdata);endmodule NOTE: This is may need changes before you use it for your lab assignment

8 Review: MIPS instruction types Three instruction formats: R-Type:register operands R-Type:register operands I-Type:immediate operand I-Type:immediate operand J-Type:for jumps J-Type:for jumps 8

9 R-Type instructions  Register-type 3 register operands: 3 register operands:  rs, rt: source registers  rd: destination register Other fields: Other fields:  op: the operation code or opcode (0 for R-type instructions)  funct: the function –together, op and funct tell the computer which operation to perform  shamt: the shift amount for shift instructions, otherwise it is 0

10 R-Type Examples Note the order of registers in the assembly code: add rd, rs, rt

11 I-Type instructions  Immediate-type 3 operands: 3 operands:  op: the opcode  rs, rt: register operands  imm: 16-bit two’s complement immediate

12 I-Type Examples Note the differing order of registers in the assembly and machine codes: addi rt, rs, imm lw rt, imm(rs) sw rt, imm(rs)

13 J-Type instructions  Jump-type 26-bit address operand (addr) 26-bit address operand (addr) Used for jump instructions (j) Used for jump instructions (j)

14 Review: Instruction Formats

15 MIPS State Elements 15 We will fill out the datapath and control logic for basic single cycle MIPS first the datapath then the control logic

16 Single-Cycle Datapath: lw  Let’s start by implementing lw instruction How does lw work? How does lw work?  STEP 1: Fetch instruction

17 Single-Cycle Datapath: lw  STEP 2: Read source operands from register file

18 Single-Cycle Datapath: lw  STEP 3: Sign-extend the immediate  NOTE: Sign Extension is done conditionally in our MIPS there are signed and unsigned instructions (e.g., ADD vs. XOR) there are signed and unsigned instructions (e.g., ADD vs. XOR)

19 Single-Cycle Datapath: lw  STEP 4: Compute the memory address Note ALUControl: ours will be different

20 Single-Cycle Datapath: lw  STEP 5: Read data from memory and write it back to register file

21 Single-Cycle Datapath: lw  STEP 6: Determine the address of the next instruction

22 Let’s be Clear: CPU is Single-Cycle!  Although the slides said “STEP” … … all those operations are performed in one cycle!!! … all those operations are performed in one cycle!!!  Let’s look at sw next …  … and then R-type instructions

23 Single-Cycle Datapath: sw  Write data in rt to memory nothing is written back into the register file nothing is written back into the register file

24 Single-Cycle Datapath: R-type instr  R-Type instructions: Read from rs and rt Read from rs and rt Write ALUResult to register file Write ALUResult to register file Write to rd (instead of rt ) Write to rd (instead of rt )

25 Single-Cycle Datapath: beq  Determine whether values in rs and rt are equal  Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4) BTA = (sign-extended immediate << 2) + (PC+4)

26 Complete Single-Cycle Processor (w/control) 26

27 Control Unit  Generally as shown below but some differences because our ALU is more sophisticated but some differences because our ALU is more sophisticated flagZ PCSrc Note: This will be 5 bits for our full-feature ALU! Note: This will be different for our full-feature ALU! Note: Zero flag is input to control, and PCSrc is generated here!

28 Review: Lightweight ALU from book F 2:0 Function 000A & B 001A | B 010A + B 011not used 100A & ~B 101A | ~B 110A - B 111SLT 28

29 Review: Lightweight ALU from book F 2:0 Function 000A & B 001A | B 010A + B 011not used 100A & ~B 101A | ~B 110A - B 111SLT 29

30 Review: Our “full feature” ALU  Our ALU from Lab 3 (with support for comparisons) Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B 1 X0 1 1 A LT B 1 X1 1 1 A LTU B X B >A X B>>>A X A & B X A | B X A ^ B X A | B 5-bit ALUFN AB Result Bidirectional Shifter Boolean Add/Sub Sub Bool Shft Math 1 0 Z Flag Flags N,V,C Bool

31 Review: R-Type instructions  Register-type 3 register operands: 3 register operands:  rs, rt: source registers  rd: destination register Other fields: Other fields:  op: the operation code or opcode (0 for R-type instructions)  funct: the function –together, op and funct tell the computer which operation to perform  shamt: the shift amount for shift instructions, otherwise it is 0

32 Controller (2 modules) module controller(input [5:0] op, funct, input flagZ, input flagZ, output memtoreg, memwrite, output memtoreg, memwrite, output pcsrc, alusrc, output pcsrc, alusrc, output regdst, regwrite, output regdst, regwrite, output jump, output jump, output [2:0] alucontrol); output [2:0] alucontrol); // 5 bit ALUFN for our ALU!! wire [1:0] aluop; // This will be different for our ALU wire [1:0] aluop; // This will be different for our ALU wire branch;// See NOTE on next slide wire branch;// See NOTE on next slide maindec md(op, memtoreg, memwrite, branch, maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop); alusrc, regdst, regwrite, jump, aluop); aludec ad(funct, aluop, alucontrol); aludec ad(funct, aluop, alucontrol); assign pcsrc = branch & (op == beq ? flagZ : ~flagZ); assign pcsrc = branch & (op == beq ? flagZ : ~flagZ); // handle both beq and bne // handle both beq and bneendmodule flagsZ PCSrc

33 Note on Controller Implementation  For Lab: we will merge the functionality of the main decoder and ALU decoder into one so, okay not to partition into two submodules so, okay not to partition into two submodules

34 Main Decoder module maindec(input [5:0] op, output memtoreg, memwrite, branch, alusrc, output memtoreg, memwrite, branch, alusrc, output regdst, regwrite, jump, output regdst, regwrite, jump, output [1:0] aluop);// different for our ALU output [1:0] aluop);// different for our ALU reg [8:0] controls; reg [8:0] controls; assign {regwrite, regdst, alusrc, assign {regwrite, regdst, alusrc, branch, memwrite, branch, memwrite, memtoreg, jump, aluop} = controls; memtoreg, jump, aluop} = controls; case(op) case(op) 6'b000000: controls <= 9'b ; //Rtype 6'b000000: controls <= 9'b ; //Rtype 6'b100011: controls <= 9'b ; //LW 6'b100011: controls <= 9'b ; //LW 6'b101011: controls <= 9'b ; //SW 6'b101011: controls <= 9'b ; //SW 6'b000100: controls <= 9'b ; //BEQ 6'b000100: controls <= 9'b ; //BEQ 6'b001000: controls <= 9'b ; //ADDI 6'b001000: controls <= 9'b ; //ADDI 6'b000010: controls <= 9'b ; //J 6'b000010: controls <= 9'b ; //J default: controls <= 9'bxxxxxxxxx; //TIP: put controls for NOP here! default: controls <= 9'bxxxxxxxxx; //TIP: put controls for NOP here! endcase endcaseendmodule Why do this? This entire coding may be different in our design

35 ALU Decoder module aludec(input [5:0] funct, input [1:0] aluop, input [1:0] aluop, output reg [2:0] alucontrol); // 5 bits for our ALU!! output reg [2:0] alucontrol); // 5 bits for our ALU!! case(aluop) case(aluop) 2'b00: alucontrol <= 3'b010; // add 2'b00: alucontrol <= 3'b010; // add 2'b01: alucontrol <= 3'b110; // sub 2'b01: alucontrol <= 3'b110; // sub default: case(funct) // RTYPE default: case(funct) // RTYPE 6'b100000: alucontrol <= 3'b010; // ADD 6'b100000: alucontrol <= 3'b010; // ADD 6'b100010: alucontrol <= 3'b110; // SUB 6'b100010: alucontrol <= 3'b110; // SUB 6'b100100: alucontrol <= 3'b000; // AND 6'b100100: alucontrol <= 3'b000; // AND 6'b100101: alucontrol <= 3'b001; // OR 6'b100101: alucontrol <= 3'b001; // OR 6'b101010: alucontrol <= 3'b111; // SLT 6'b101010: alucontrol <= 3'b111; // SLT default: alucontrol <= 3'bxxx; // ??? default: alucontrol <= 3'bxxx; // ??? endcase endcase endmodule This entire coding will be different in our design

36 Control Unit: ALU Decoder ALUOp 1:0 Meaning 00Add 01Subtract 10Look at Funct 11Not Used ALUOp 1:0 FunctALUControl 2:0 00X010 (Add) X1X110 (Subtract) 1X ( add ) 010 (Add) 1X ( sub ) 110 (Subtract) 1X ( and ) 000 (And) 1X ( or ) 001 (Or) 1X ( slt ) 111 (SLT) This entire coding will be different in our design 36

37 Control Unit: Main Decoder InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 R-type … lw … sw X101X… beq X010X… 37

38 Note on controller  The actual number and names of control signals may be somewhat different in our/your design compared to the one given in the book compared to the one given in the book because we are implementing more features/instructions because we are implementing more features/instructions SO BE VERY CAREFUL WHEN YOU DESIGN YOUR CPU! SO BE VERY CAREFUL WHEN YOU DESIGN YOUR CPU!

39 Single-Cycle Datapath Example: or 39

40 Extended Functionality: addi  No change to datapath

41 Control Unit: addi InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 R-type … lw … sw X101X… beq X010X… addi … 41

42 Adding Jumps: j 42

43 Control Unit: Main Decoder InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 Jump R-type … lw … sw X101X… beq X010X… j 0XXX0XXX1 43

44 Summary  We learned about a complete MIPS CPU  NOTE: Many details are different… … from what you will implement in the lab … from what you will implement in the lab our lab MIPS has more features our lab MIPS has more features every single line of Verilog you take from these slides must be carefully vetted! every single line of Verilog you take from these slides must be carefully vetted!  Next class: We will look at performance of single-cycle MIPS We will look at performance of single-cycle MIPS We will look at multi-cycle MIPS to improve performance We will look at multi-cycle MIPS to improve performance  Next lab: Implement single-cycle CPU! Implement single-cycle CPU!


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