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Digital Codes Coding Gain For a given Bit error Rate, Coding Gain is defined as the increase required in C/N such that un-coded data yields the same BER as Coded data. Standard Codes (covered in CEC 220) CCITT-2/ITU ARQ ASCII EBCDIC Gray

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Reed Solomon Code Properties Byte Oriented Block Code m : bits per byte k : information bytes per block n = 2 m - 1 : total bytes per block t : number of byte error corrections possible n – k = 2t : required redundancy bytes r = k/n : code “rate” Example: Determine the block properties of an RS code with m = 6 bits/byte, capable of correcting t = 4 byte errors per block. n = 2 6 – 1 = 63 bytes/block = 378 bits/block n - k = 2t = 8 bytes = 48 redundancy bits k = n – 2t = 55 data bytes = 330 data bits r = k/n = 55/63 = rate 0.873

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Reed Solomon Codes (cont) A “byte error” is byte containing a single bit error. Multiple bit errors within a byte cannot be corrected, so RS codes are vulnerable to channel interruptions resulting in “burst errors.” Bit ordering over several coded blocks are often shuffled at the transmitter in a prescribed way and un- shuffled at the receiver so that burst errors are dispersed over several blocks. This is known as Data Interleaving.

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BCH Code Properties Block/Word oriented Code Cyclic (polynomial) Code: encoding/decoding is accomplished using shift registers and Modulo 2 addition (XOR). cnumber of correctible bits per word n = 2 i – 1total bits per word k > n - cinumber of data bit per word Example: Determine the block properties of a BCH code with k = 64 bits/word, capable of correcting c = 4 bit errors per word. n = 2 i – 1 < ci +k < 4i + 64 i min = 7 n min = 127 Note: for i = 7 (n = 127), we could have c = 5 and k = 92

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Convolutional Codes D Q Clock Data + + 4 Symbol Modulator Transmitted Symbols Received Symbols Data Viterbi Decoder Encoder (State Machine) The Viterbi decoder uses the input symbols to construct the most likely sequence of encoder states, and deduces the data sequence therefrom. Q0Q0 Q1Q1 Q2Q2

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001 11 000 00 101 00 010 01 100 11 011 10 110 10 111 01 Data = 1 Data = 0 State Diagram for Example Encoder y1y2y1y2 Q0Q0 Q1Q1 Q2Q2 Q2Q1Q0y1y2Q2Q1Q0y1y2 Data State Template

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001 11 000 00 101 00 010 01 100 11 011 10 110 10 111 01 Data = 1 Data = 0 Decoding Example

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1 SNS COLLEGE OF ENGINEERING Department of Electronics and Communication Engineering Subject: Digital communication Sem: V Cyclic Codes.

1 SNS COLLEGE OF ENGINEERING Department of Electronics and Communication Engineering Subject: Digital communication Sem: V Cyclic Codes.

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