1. STM32VL- Training
Esprit 2012
V1.0

2. CONTENTS PART I : CORTEX-M3 PART II : STM32F100 device
PART III : STM32 Value line Discovery Kit

3. PART - I
CORTEX M3

4. CONTENTS Objectives Introduction Cortex-M3 Processor
Cortex M3 interrupt handling
Cortex-M3 Memory Map
Power Management
System Timer (SysTick)
Debug Capabilities

5. OBJECTIVES Familiarize with Cortex M3
At the end of the part you will be able to List the main features of the Cortex M3

6. CONTENTS Objectives Introduction Cortex-M3 Processor
Cortex M3 interrupt handling
Cortex-M3 Memory Map
Power Management
System Timer (SysTick)
Debug Capabilities

7. What is ARM(Advanced Risc Machines)?
ARM is an UK company that designs innovative 32-bit microprocessors
ARM leads the world of RISC microprocessor cores
ARM develops directly and through partnership the tools, systems and services to support its architecture.

8. Why use an ARM-based processor?
Most popular 32-bit core
Becoming an industrial standard like the C51
Compatible leading edge core roadmap
ARM7 -> ARM9 /10->CortexM3, M4,…
Large number of product choices
Multiple vendors means a large choice

9. Why use an ARM-based processor?
Sales in billions of dollars

10. Why Cortex M3? RISC Processor core Low power modes
Tools and RTOS support

11. Why Cortex M3?
More Than 28 company
ST, NXP, Atmel, Samsung…
Cortex-A Series, applications processors for complex OS and user applications.
Cortex-R Series, real-time systems profile.
Cortex-M Series, microcontroller profile optimized for cost-sensitive applications..
The number at the end of the Cortex name refers to the relative performance level, with 1 the lowest and 8 the highest.

12. ARM Cortex-M code size advantage explained

13. Industry standard

14. CONTENTS Objectives Introduction Cortex-M3 Processor
Cortex M3 interrupt handling
Cortex-M3 Memory Map
Power Management
System Timer (SysTick)
Debug Capabilities

15. Cortex-M3 Processor(1/2)
Hierarchical processor integrating core and advanced system peripherals
Cortex-M3 Processor
Cortex-M3 core
Configurable interrupt controller
Bus matrix
Advanced debug components(ETM…)
Optional MPU(Not available in STM32F10x)
Harvard architecture
3-stage pipeline prediction
Thumb®-2
ALU w. H/W divide and single cycle multiply

16. Cortex-M3 Processor(2/2)
Non Maskable
Interrupt
3-Stage Pipeline, Harvard Architecture,
Thumb-2 ISA (or Thumb) K* Gates
1-240 Configurable
Interrupts
with Configurable Priority
Levels
SWD or JTAG
Breakpoints
Data Watchpoints
& Trace
* Preliminary gate counts & power consumption based on initial implementation
Gate Counts are based on TSMC 0.18 at 50MHz
Optional ETM & MPU gate counts not included
Cortex M3 Total 60k* Gates

17. Cortex-M3 Processor Main Features
ARM v7M Architecture
Thumb-2 Instruction Set Architecture
Mix of 16 and 32 bit instructions for very high code density
Harvard architecture
Separate I & D buses allow parallel instruction fetching & data storage
Integrated Nested Vectored Interrupt Controller (NVIC) Vector Table is addresses.
Integrated Bus Matrix
Data memory management
3 Stage Pipeline
Integrated System Timer (SysTick) for Real Time OS

18. Data Memory management (1/7)
Cortex-M3 includes two technologies to reduce Data memory requirements:
Unaligned Data Support
Atomic Bit Banding
These technologies can dramatically improve data (SRAM) memory utilization, potentially enabling silicon designers and users to reduce the amount of SRAM required and dramatically impacting silicon usage.

19. Data Memory management(2/7)
Unaligned Data Support:
Other Core does not support unaligned data
ARM Cortex-M3 supports unaligned data that can improve SRAM utilization
Long (32)
Long (32)
Long (32)
Long (32)
short (16)
short (16)
short (16)
short (16)
Char
Char
Char
Char
Data aligned on word boundaries
Char
Char
Char
Char
Unused (wasted) space
Free space Can be used
Reduces SRAM Memory Requirements By Over 50%
Less Memory - LowER Cost devices

20. Data Memory management(3/7)
long (32)
int (16)
char (8)
int (16)c
… long
int (16)
char (8)
int (16)c
… long (32)
long (32)
long (32) …
long …
Structure management example
32bit machine which does not support unaligned data
Data aligned
Unused (wasted) space
Free space for the rest of the application
Reduces SRAM Memory Requirements By Over 25%

21. Data Memory management(4/7)
Bit Banding:
Read byte (RAM, register) 1
Disable external events
Mask and modify bit element X
Write byte (RAM, register)
Enable external events
Traditional method
Speed and code size optimized
Cortex-M3 implementation b0
b31
32bit
@Rbase+N
example: h to 200FFFFFh
VIRTUAL
aliased
bit banding
image
REAL memory
♦ Bit Banding done by bus matrix.
♦ Single instruction Read/Modify/Write (no more masking).
♦ No new instruction set  Use standard data one (AND, OR, XOR…).
Optimized RAM, peripherals and IOs registers accesses Easy multi-task semaphore management

22. Data Memory management(5/7)
32MB alias region
1MB Peripheral bit-band region

23. Data Memory management(6/7)
Bit Banding formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)
where:
bit_word_addr: is the address of the word in the alias memory region that maps to the targeted bit.
bit_band_base is the starting address of the alias region (0x )
byte_offset is the number of the byte in the bit-band region that contains the targeted bit
bit_number is the bit position of the targeted bit(0-7) .
Example -1:
How to map bit 2 of the byte located at Peripheral X address 0x in the alias region (Peripheral X based address is 0x ):

24. Data Memory management(7/7)
Solution:
0x = 0x (0x300*32) + (2*4).
Writing to address 0x has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x
Reading address 0x returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x (0x01: bit set; 0x00: bit reset).
For more information on Bit-Banding, please refer to the Cortex™-M3 Technical Reference Manual.

25. Instruction Pipeline(1/3)
PC points to fetch stage:
FETCH
Instruction fetched from memory
DECODE
Instruction decoded
Register(s) read from Register Bank
Shift and ALU operation or memory access
Write register(s) back to Register Bank
EXECUTE

26. Instruction Pipeline(2/3)
Optimal Pipelining:
Cycle 1 2 3 4 5 6 7 8 9
Operation
ADD F D E
SUB
ORR
AND
EOR
F- Fetch D - Decode E - Execute
All operations here are registers (single cycle execution)
In this example it takes 6 cycles to execute 6 instructions
Clock cycles per Instructions (CPI) = 1

27. Instruction Pipeline(3/3)
Flushing :
A flush of the pipeline can occur because of
A Branch
An exception
A breakpoint
Branch Pipeline Example:
Cycle E D F 6 5 4 3 2 1 9 8 7
Address Operation
0x B 0x8FEC
0x SUB
0x ORR
0x8FEC AND
0x8FEE ORR
0x8FF0 EOR
F- Fetch D - Decode E - Execute

28. Register Set(1/2)
Registers R0-R12 are simple registers that can be used to hold program variables.
Registers R13-R15 have special functions within the Cortex CPU.
R13: Register R13 is used as the stack pointer
R14: called the link register. used to store the return address when a call is made to a procedure
R15: is the program counter
xPSR:The Program Status Register contains status fields for instruction execution
Register Set R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
R10
R11
R12
R13(SP)
R14(LR)
R15 (PC)
xPSR

29. CONTENTS Objectives Introduction Cortex-M3 Processor
Cortex M3 interrupt handling
Cortex-M3 Memory Map
System Timer (SysTick)
Debug Capabilities

30. Interrupt Handling
The Cortex-M3 processor integrates an advanced Nested Vectored Interrupt Controller (NVIC)
The NVIC supports up to 240 dynamically reprioritizes interrupts each with up to 256 levels of priority
Supports advanced features for next generation real-time applications:
Tail-chaining of pending interrupts
Interrupt Pre-emption
Late Arrival

31. Interrupt Response- Tail Chaining(1/3)
IRQ1
Highest
IRQ2
42 CYCLES
ARM7
Interrupt handling in assembler code
PUSH
ISR 1
POP
PUSH
ISR 2
POP 26 16 26 16
Tail-chaining
Cortex-M3
Interrupt handling in HW
PUSH
ISR 1
ISR 2
POP
65% Saving in Clock Cycles 12 6 12
6 CYCLES
ARM7
26 cycles from IRQ1 to ISR1 entered
Up to 42 cycles
42 cycles from ISR1 exit to ISR2 entry
16 cycles to return from ISR2
Cortex-M3
12 cycles from IRQ1 to ISR1 entered
12 cycles
6 cycles from ISR1 exit to ISR2 entry
12 cycles to return from ISR2

32. Interrupt Response – Preemption(2/3)
IRQ1
Highest
IRQ2
42 CYCLES
ARM7
ISR 1
POP
PUSH 2
ISR 2
POP 16 26 16
Cortex-M3
ISR 1
POP
ISR 2
POP 12 1- 12 6
7-18 CYCLES

33. Interrupt Response – Late Arriving(3/3)
Less than 12 cycle
IRQ1
Highest
IRQ2
ARM7
PUSH
PUSH
ISR 1
POP
ISR 2
POP 26 26 16 16
Cortex-M3
PUSH
ISR 1
ISR 2
POP 6 12
Tail-Chaining

34. Interrupt Response – Lab
More than12 cycle
Highest
NMI
IRQ1
IRQ2
IRQ3
Less than12 cycle
PUSH
PUSH
NMI
ISR 1
POP
ISR 2
ISR 3
POP
ISR 2 Starts
Push for ISR1 begins
Pre-empted by NMI
New instruction fetch in
parallel minimises time to NMI
Cortex-M3
Following NMI processor tail-chains into ISR1
ISR2 Completed
Pop only occurs on return to “Main”

35. NVIC Registers
Each interrupt input has several registers to control it
Enable/Disable Bit
Enable or disable the interrupt
Can be set, cleared or read
Pending Bit
If the pending bit is set, then the interrupt is pending
A pending interrupt can only be taken (become active) if it is enabled and it has sufficient priority to run
Pending bit can be set, cleared or read
Active Bit
A bit is set if the interrupt is executing or “active-stacked”
“Active-stacked” means the interrupt was executing, but was pre-empted by another higher-priority interrupt
Active register is normally read only
Priority field
priority management for each interrupt

36. Cortex-M3 Exception Types
No.
Exception Type
Priority
Type of Priority
Descriptions 1
Reset
-3 (Highest)
fixed 2
NMI -2
Non-Maskable Interrupt 3
Hard Fault -1
Default fault if other hander not implemented 4
MemManage Fault
settable
MPU violation or access to illegal locations 5
Bus Fault
Fault if AHB interface receives error 6
Usage Fault
Exceptions due to program errors
7-10
Reserved
N.A. 11
SVCall
System Service call 12
Debug Monitor
Break points, watch points, external debug 13 14
PendSV
Pendable request for System Device 15
SYSTICK
System Tick Timer 16
Interrupt #0 7
External Interrupt #0 ……
…………………..
………………
256
Interrupt#240
247
External Interrupt #240

37. CONTENTS Objectives Introduction Cortex-M3 Processor
Cortex M3 interrupt handling
Cortex-M3 Memory Map
Power Management
System Timer (SysTick)
Debug Capabilities

38. Cortex-M3 Memory Map

39. CONTENTS Objectives Introduction Cortex-M3 Processor
Cortex M3 interrupt handling
Cortex-M3 Memory Map
Power Management
System Timer (SysTick)
Debug Capabilities

40. Power Management Optimized RUN mode CORE power consumption
8bit Microcontroller like power mode management
SLEEP NOW
♦ “Wait for Interrupt” instructions to enter low power mode
No more dedicated control register settings sequence
♦ “Wait for Event” instructions to enter low power mode
No need of Interrupt to wake-up from sleep
Rapid resume from sleep
SLEEP on EXIT
♦ Sleep request done in interrupt routine
♦ Low power mode entered on interrupt return
Very fast wakeup time
DEEP SLEEP
♦ Long duration sleep
From product side: PLL can be stopped or shuts down the power to digital parts of the system
Enables low power consumption
Optimized RUN mode CORE power consumption

41. CONTENTS Objectives Introduction Cortex-M3 Processor
Cortex M3 interrupt handling
Cortex-M3 Memory Map
Power Management
System Timer (SysTick)
Debug Capabilities

42. System Timer (SysTick)
Flexible system timer
24-bit self-reloading down counter with end of count interrupt generation
2 configurable Clock sources
Suitable for Real Time OS or other scheduled tasks
In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8 (provided externally by the Reset Clock Control )

43. CONTENTS Objectives Introduction Cortex-M3 Processor
What is ARM ?
Why use an ARM-based processor?
Cortex-M3 Processor
Cortex-M3 Processor Main Features
Data Memory
Instruction Pipeline
Write Buffer
Privilege, Modes, Stacks and Register Set
Cortex M3 interrupt handling
Exception/Interrupt Handling,
NVIC Registers
Cortex-M3 Exception Types
Vector Table
Cortex-M3 Memory Map
Power Management
System Timer (SysTick)
Debug Capabilities

44. Debug Capabilities Three solutions are possible :
SWD
More pins available
for the application
ETM
JTAG
Joint Test Action Group easy flashed application debugging
♦ 8 hardware breakpoints
Serial Wire Debug for targeted low bandwidth data trace
Enhanced Thematic Mapper capability for better real time debugging
♦ Instruction trace only

45. 5 reasons to choose Cortex-M3
Performance
Real time
5 reasons to choose Cortex-M3
Power Management
Optimized Memory
Powerful Debugging

46. PART - II
STM32F10x Device

47. CONTENTS Objectives STM32F10x Device STM32F10x System Peripherals
Block Diagram
Memory mapping and boot modes
System Architecture
STM32F10x System Peripherals
Main features
STM32F10x Minimum External Components
STM32F10x standard peripheral Library
What is CMSIS?
Package organization
STM32F10xxx standard peripheral library architecture
Coding conventions
Using the Library

48. OBJECTIVES Familiarize with STM32F10x device
At the end of the training you will be able to
List the main features of the STM32F10x system peripherals
Configure the standard library environment
Develop your applications using the STM32F10x standard library

49. CONTENTS Objectives STM32F10x Device STM32F10x System Peripherals
Block Diagram
Memory mapping and boot modes
System Architecture
STM32F10x System Peripherals
Main features
STM32F10x Minimum External Components
STM32F10x standard peripheral Library
What is CMSIS?
Package organization
STM32F10xxx standard peripheral library architecture
Coding conventions
Using the Library

50. More choice with STM32 series
The general purpose F‑1 series
addresses a wide range of applications,
from the lowest price‑sensitive design to
the computing intensive, high memory
Footprint
Get the highest performance with the
F‑2 series for computing intensive
application and advanced connectivity.
The F‑2 series maintains the compatibility
with the F‑1 series.
Get the highest performance with the
Design ultra‑low‑power applications with
the L‑1 series for those who are power
conscious and seek the absolute lowest
energy consumption. The L‑1 series
maintains the compatibility with the F‑1
series.

51. STM32 portfolio based on F1 series

52. STM32 Value line 16K-32KBytes block diagram
CORTEXTM-M CPU 24 MHz
4kB SRAM
ARM® Peripheral Bus 2
(max 24MHz)
1 x I2C
1 x USART/LIN Smartcard / IrDa Modem Control
37/51 I/Os
Up to 16 Ext. ITs
Flash I/F
16kB - 32kB Flash Memory
JTAG/SW Debug
XTAL oscillators 32KHz + 4~25MHz
Power Supply Reg 1.8V POR/PDR/PVD
DMA 7 Channels
Nested vect IT Ctrl
1 x USART/LIN Smartcard/IrDa Modem Control
1 x SPI
Bridge
ARM Lite Hi-Speed Bus Matrix / Arbiter (max 24MHz)
Int. RC oscillators 40KHz + 8MHz
PLL
Clock Control
RTC / AWU
ARM® Peripheral Bus 1
20B Backup Data
1 x 12-bit ADC
up to 16 channels
Temperature Sensor
2 x Watchdog (independent & window)
5 x 16-bit timer
1 x CEC
2-channel 12-bit DAC
1 x Systick Timer
1 x 16-bit PWM Synchronized AC Timer
Core and operating conditions
ARM® Cortex™-M DMIPS/MHz up to 24 MHz
2.0 V to 3.6 V range
-40 to +105 °C
Rich connectivity
5 communications peripherals
Advanced analog
12-bit1.2 µs conversion time ADC
Dual channel 12-bit DAC
Enhanced control
16-bit motor control timer
5x 16-bit PWM timers
LQFP48, LQFP/BGA64

53. STM32 Value line 64K-128KBytes block diagram
CORTEXTM-M3 CPU 24 MHz
ARM® Peripheral Bus2
(max 24MHz)
2 x I2C
1 x SPI
2 x USART/LIN Smartcard / IrDa Modem Control
37/51/80 I/Os
Up to 16 Ext. ITs
JTAG/SW Debug
Power Supply Reg 1.8V POR/PDR/PVD
DMA 7 Channels
Nested vect IT Ctrl
1 x USART/LIN Smartcard/IrDa Modem Control
Bridge
1 x Systick Timer
ARM® Lite Hi-Speed Bus Matrix / Arbiter (max 24MHz)
RTC / AWU
ARM® Peripheral Bus1
XTAL oscillators 32KHz + 4~25MHz
Int. RC oscillators 40KHz + 8MHz
PLL
8kB SRAM
Flash I/F
64kB - 128kB Flash Memory
Clock Control
20B Backup Data
1 x 12-bit ADC up to16 channels
Temperature Sensor
2 x Watchdog (independent & window)
6 x 16-bit Timer
1 x CEC
2-channel 12-bit DAC
1 x 16-bit PWM Synchronized AC Timer
Core and operating conditions
ARM® Cortex™-M DMIPS/MHz up to 24 MHz
2.0 V to 3.6 V range
-40 to +105 °C
Rich connectivity
8 communications peripherals
Advanced analog
12-bit1.2 µs conversion time ADC
Dual channel 12-bit DAC
Enhanced control
16-bit motor control timer
6x 16-bit PWM timers
LQFP48, LQFP/BGA64, LQFP100

54. STM32 Value line 256K-512KBytes block diagram
CORTEXTM-M CPU 24 MHz
ARM® Peripheral Bus 2
(max 24MHz)
2 x I2C
4 x USART/LIN Smartcard / IrDa Modem Control
51/80/112 I/Os
Up to 16 Ext. ITs
FSMC
SRAM/ NOR/ LCD parallel interface
JTAG/SW Debug
Power Supply Reg 1.8V POR/PDR/PVD
DMA up to 12 Channels
Nested vect IT Ctrl
1 x USART/LIN Smartcard/IrDa Modem Control
1 x SPI
Bridge
1 x Systick Timer
ARM ® Lite Hi-Speed 36us Matrix / Arbiter (max 24MHz)
RTC / AWU
ARM® Peripheral Bus 1
XTAL oscillators 32KHz + 4~25MHz
Int. RC oscillators 40KHz + 8MHz
PLL
24KB-32kB SRAM
Flash I/F
256KB-512kB Flash Memory
Clock Control
84B Backup Data
2-channel 12-bit DAC
1 x 12-bit ADC up to 16 channels
Temperature Sensor
2 x Watchdog (independent & window)
10 x 16-bit Timer
2 x SPI
1 x CEC
1 x 16-bit PWM Synchronized AC Timer
Core and operating conditions
ARM® Cortex™-M DMIPS/MHz up to 24 MHz
2.0 V to 3.6 V range
-40 to +105 °C
Rich connectivity
11 communications peripherals
FSMC
SRAM, NOR, memories support.
LCD Parallel interface 8/16-bit
Intel 8080 and Motorola 68K
Enhanced control
16-bit motor control timer
10x 16-bit PWM timers
LQFP64, LQFP100, LQFP144

55. Memory Mapping and Boot Modes
Addressable memory space of 4 GBytes
RAM : up to 32 kBytes
FLASH : up to 512 kBytes
Boot modes:
Depending on the Boot configuration
- Embedded Flash Memory
- System Memory
- Embedded SRAM Memory
is aliased
0xFFFF FFFF
Reserved
0xE
0xE00F FFFF
Cortex-M3 internal peripherals
0xE
Flash
SystemMemory
Reserved
Option Bytes
BOOT Mode
Selection Pins
Boot Mode
Aliasing
BOOT1
BOOT0 x
User Flash
User Flash is selected as boot space 1
SystemMemory
SystemMemory is selected as boot space
Embedded SRAM
Embedded SRAM is selected as boot space
0x1FFF F80F
Reserved
0x1FFF F800
0x1FFF F7FF
0x1FFF F000
Peripherals
0x0801 FFFF 0x
Reserved 0x
SRAM 0x
SystemMemory: contains the Bootloader
used to re-program the FLASH through USART1.
Reserved
CODE 0x

56. Buses are not overloaded with data movement tasks
System Architecture
Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA
BusMatrix added to Harvard architecture allows parallel access
Efficient DMA and Rapid data flow
Direct path to SRAM through arbiter, guarantees alternating access
Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer
I-bus
CORTEX-M3
Master 1
FLASH
Flash I/F
D-bus
SRAM
Slave
BusMatrix
Peripheral Bus APB2
APB2
GP-DMA
Master 2
AHB
AHB-APB2
AHB-APB1
APB1
Peripheral Bus APB1
Arbiter
Bridges
Buses are not overloaded with data movement tasks

57. CONTENTS Objectives STM32F10x Device STM32F10x System Peripherals
Block Diagram
Memory mapping and boot modes
System Architecture
STM32F10x System Peripherals
Main features
STM32F10x Minimum External Components
STM32F10x standard peripheral Library
What is CMSIS?
Package organization
STM32F10xxx standard peripheral library architecture
Coding conventions
Using the Library

58. STM32F101x Series Block Diagram
CORTEXTM-M CPU 24 MHz
ARM® Peripheral Bus
(max 24MHz)
2 x I2C
4 x USART/LIN Smartcard / IrDa Modem Control
51/80/112 I/Os
Up to 16 Ext. ITs
FSMC
SRAM/ NOR/ LCD parallel interface
JTAG/SW Debug
Power Supply Reg 1.8V POR/PDR/PVD
DMA up to 12 Channels
Nested vect IT Ctrl
1 x USART/LIN Smartcard/IrDa Modem Control
1 x SPI
Bridge
1 x Systick Timer
ARM ® Lite Hi-Speed 36us Matrix / Arbiter (max 24MHz)
RTC / AWU
XTAL oscillators 32KHz + 4~25MHz
Int. RC oscillators 40KHz + 8MHz
PLL
24KB-32kB SRAM
Flash I/F
256KB-512kB Flash Memory
Clock Control
84B Backup Data
2-channel 12-bit DAC
1 x 12-bit ADC up to 16 channels
Temperature Sensor
2 x Watchdog (independent & window)
10 x 16-bit Timer
2 x SPI
1 x CEC
1 x 16-bit PWM Synchronized AC Timer

59. Power Control (PWR) and Backup Domain (BKP)

60. Power Supply Power Supply Schemes
VDD = 2.0 to 3.6 V: External Power Supply for I/Os and the internal regulator.
VDDA = 2.0 to 3.6 V: External Analog Power supplies for ADC, Reset blocks, RCs and PLL.
 ADC working only if VDDA ≥ 2.4 V
VBAT = 1.8 to 3.6 V: For Backup domain when VDD is not present.
A/D converter
Temp. sensor
Reset block
PLL
VDDA domain
LSE crystal 32K osc
BKP registers
RCC BDCR register
RTC
Backup domain
Core
Memories
Digital
peripherals
V18 domain
VDD domain
STANDBY circuitry
(Wake-up logic,
IWDG, RCC CSR reg)
Voltage Regulator
I/O Rings
Low Voltage Detector
VREF-
VREF+
VDDA
VSSA
VSS
VDD
VBAT

61. Power On Reset / Power Down Reset
Integrated POR(Power On Reset )/ PDR(Power Down Reset ): circuitry guarantees proper product reset when voltage is not in the product guaranteed voltage range (2V to 3.6V)
No need for external reset circuit
POR and PDR have a typical hysteresis of 40mV
VDD
Vtrh
POR
Vtrl
40mv hysteresis
PDR
Tempo 2ms
Reset
Vtrl min 1.8V / Vtrh max 2V

62. Programmable Voltage Detector (PVD)
Enabled by software
Monitor the VDD power supply by comparing it to a threshold
Threshold configurable from 2.2V to 2.9V by step of 100mV
VDD
100mv hysteresis
PVD
Output
PVD Threshold
Threshold

63. Backup Domain Backup Domain contains VBAT independent voltage supply
RTC (Counter, Prescaler and Alarm mechanism)
Separate 32KHz Osc (LSE) for RTC
20-byte user backup data
RCC BDSR register: RTC source clock selection and enable + LSE config
 Reset only by Backup domain RESET
VBAT independent voltage supply
Automatic switch-over to VBAT when VDD goes lower than PDR level
No current sunk on VBAT when VDD present
Tamper detection: resets all user backup registers
Configurable level: low/high
Configurable interrupt generation
Backup domain
32KHz OSC
(LSE)
RTC
20 byte
data
ANTI_TAMP
VBAT
VDD
RCC BDSR
reg
power switch

64. Low Power Modes STM32F10x Low Power modes: uses CortexM3 Sleep modes
SLEEP, STOP and STANDBY modes
 The reset circuitry, POR/PDR, is active in STANDBY and STOP modes
Feature
STM32F10x typ (*)
Consumption in RUN mode w/ execute from Flash on internal RC and peripherals clock ON
4.9mA
Consumption in RUN mode w/ execute from Flash on PLL 24 MHz
(HSE : external clock = 8MHz) and peripherals clock ON
36mA
(HSE : external clock = 8MHz) and peripherals clock OFF
27mA
STOP w/ Voltage Regulator in low power
Low speed and high-speed internal RC oscillators and high-speed oscillator OFF(no independent watchdog)
14µA
STANDBY w/ low-speed oscillator and RTC OFF
Low-speed internal RC oscillator and independent watchdog OFF
2µA
RTC on VBAT
1.4 µA
(*) : Typical values are measured at TA = 25 °C, VDD/VBAT = 3.3 V.

65. CONTENTS Objectives STM32F10x Device STM32F10x System Peripherals
Block Diagram
Memory mapping and boot modes
System Architecture
STM32F10x System Peripherals
Main features
STM32F10x Minimum External Components
STM32F10x standard peripheral Library
What is CMSIS?
Package organization
STM32F10xxx standard peripheral library architecture
Coding conventions
Using the Library

66. STM32F10x Minimum External Components
Built-in Power Supply Supervisor reduces need for external components
Filtered reset input, integrated POR/PDR circuitry, programmable Voltage Detector (PVD).
Embedded 8 MHz High-Speed Internal (HSI) RC oscillator can be used as main clock
Optional main crystal drives entire system
Inexpensive 4-16 MHz crystal drives CPU, all peripherals
Optional kHz crystal needed additionally for RTC, can run on 40KHz Low Speed Internal (LSI) RC oscillator
Only 7 mandatory external passive components for base
system on LQFP100 package!
Application Note is available from
AN2586: STM32F10xxx Hardware development : getting started

67. CONTENTS Objectives STM32F10x Device STM32F10x System Peripherals
Block Diagram
Memory mapping and boot modes
System Architecture
STM32F10x System Peripherals
Main features
STM32F10x Minimum External Components
STM32F10x standard peripheral Library
What is CMSIS?
Package organization
STM32F10xxx standard peripheral library architecture
Coding conventions
Using the Library

68. What is CMSIS? Definition: CMSIS layer structure
The Cortex-M3™ Microcontroller Software Interface Standard (CMSIS) is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems and middleware components. For more details, please refer to
CMSIS layer structure

69. Package organization

70. STM32 Firmware Library User Manual
Main page

71. STM32 Firmware Library User Manual

72. STM32F10xxx standard peripheral library architecture
- STM32 interrupt IRQ list/ Specific options for the Cortex-M3 core
- STM32 peripheral memory mapping and physical register address definition
- Configuration options …
User application
Cortex-M3 exceptions
Peripheral header file
Include NVIC and
SysTick drivers
Low-level & API functions to
Perform basic operations
offered by the peripheral

73. Coding conventions All firmware is coded in ANSI-C
Strict ANSI-C for all library peripheral files
Relaxed ANSI-C for projects & Examples files.
PPP is used to reference any peripheral acronym, e.g. TIM for Timer.
Registers & Structures
FW library registers have the same names as in STM32F10x Datasheet & reference manual.
All registers hardware accesses are performed through a C structures :
Improve code re-use : e.g. the same structure to handle and initialize 3 USARTs.

74. Using the Library (1/4)
1) Before configuring a peripheral, you have to enable its clock by calling one of the following functions:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_PPPx , ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_PPPx , ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PPPx , ENABLE);
2) PPP_DeInit(..) function can be used to set all PPP’s peripheral registers to their reset values:
PPP_DeInit(PPPx);
3) If after peripheral configuration, the user wants to modify one or more peripheral settings he should proceed as following:
PPP_InitStucture.memberX = valX;
PPP_InitStructure.memberY = valY;
PPP_Init(PPPx, &PPP_InitStructure);

75. Using the Library (2/4)
At this stage the PPP peripheral is initialized and can be enabled by making a call to PPP_Cmd(..) function: PPP_Cmd(PPPx, ENABLE);
Note: This function is used only for communication peripherals like UART, SPI, …
To access the functionality of the PPP peripheral, the user can use a set of dedicated functions. These functions are specific to the peripheral and for more details refer to STM32F10x Firmware Library User Manual.
Example of GPIO
Functions available

76. Using the Library (3/4) UART1 configuration example :
/* Enable USART1 Clock */
RCC_APB2PeriphClockCmd( USART1, ENABLE );
/* set all UART1’s peripheral registers to their reset values */
USART_DeInit( USART1 ) ;
/* USART1 configuration */
/* USART1 configured as follow:
- BaudRate = baud
- Word Length = 8 Bits
- One Stop Bit
- Even parity
- Hardware flow control disabled (RTS and CTS signals)
- Receive and transmit enabled */
USART_InitStructure.USART_BaudRate = 9600;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_Even;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
/* Configure USART1 */
USART_Init( USART1, &USART_InitStructure);
/* Enable USART1 */
USART_Cmd( USART1, ENABLE );
USART 1 is ready now …

77. Files to be modified by the user:
Using the Library (4/4)
Files to be modified by the user:
stm32f10x_conf.h
/* Includes */
/* Uncomment the line below to enable peripheral header file inclusion */
/* #include "stm32f10x_adc.h" */
/* #include "stm32f10x_bkp.h" */
/* #include "stm32f10x_can.h" */ …
main.c
#include "stm32f10x.h“
int main(void) {
...
GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET); … }
stm32f10x_It.h
/* Exported functions */
void NMI_Handler(void);
void HardFault_Handler(void); …
stm32f10x.h
/* Uncomment the line below according to the target STM32 device used in your application */
#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD)
/* #define STM32F10X_LD */ /*!< STM32 Low density devices */…
#endif …
/* STM32F10x Interrupt Number Definition*/
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
stm32f10x_It.c
#include "stm32f10x_it.h" …
void EXTI1_IRQHandler(void) {
GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET); }

78. STM32 Value line Discovery Kit
PART - III
STM32 Value line Discovery Kit

79. STM32 Value line Discovery Kit
Microcontroller Division of MMS Group
June, 2010

80. The cheapest and quickest way to discover the STM32
Everything included for a quick start with the STM32 Value Line
Price: $9.90 (RRP)
Order code: STM32VLDISCOVERY
Available NOW from ST and Distributors
In circuit ST-LINK debugger / programmer included to debug Discovery kit applications or other target board applications.
Ideal for quick evaluation, learning or prototyping
Dedicated web site
Examples ready to run
Schematics
Forums and more… 80

81. STM32 Value line Discovery Board
A compact “all in one board”
The debugger “ST-link” is on the board itself
Few leds and button for immediate usage
The extension connector will all STM32 pins enable building more complex applications by using an extension board
The board can be used as an independent ST-link for your own board if needed
ST-LINK
SWD connector
84mm
STM32F100RBT6B
User button
Led Blue
Led Green
42mm
Extension connector
On each side 81

82. Tools and Software Development Toolchain support
Free Atollic TrueSTUDIO® lite version with
unlimited code-size and usage-time.
IAR EWARM
KEIL MDK-ARM
Software examples available at for a quick start to evaluate and develop with the STM32 Value line 82

83. Features and Benefits
Feature
Benefit
STM32F100RBT6B microcontroller
Discover STM32 with STM32 Value line, including 128-Kbyte Flash, 8-Kbyte RAM in a 64-pin LQFP  
Self powered by USB cable between PC and STM32 Value line Discovery
Immediate plug-and-play demonstration
Can supply target application with 5 V and 3 V
Adapts the demo to the future application environment
On-board ST-Link with USB interface for programming and debugging
Non-intrusive debug with the in-circuit debugger present on STM32 Value line Discovery.
Selection mode switch to use the kit as a standalone ST-Link (with SWD connector)
The kit can be used as an ST-link for your own board
Extension header for all QFP64 I/Os
Ideal for prototyping and easy probing.  Enable quick connection to a prototyping board
Development toolchains from partners
Complete kit enabling full software development, no need for additional software.
Large number of free, downloadable ready-to-use software examples
Fast startup, accelerate your developments.
More than 37 Videos are available on YouTube web site.
example: link : 83

84. STM32F100xx Value Line necessary docs
RM0041 (Reference Manual): Peripherals description…
PM0063 (Flash Programming Manual): Flash description…
Product Datasheet STM32F100x468B-B: Electrical parameters…
STM32F10x Standard Peripheral Library V3.3.0: STM32 value Line Firmware library, examples…
AN3268 (STM32VLDISCOVERY firmware package): STM32 discovery Firmware library…
UM0919 (STM32VLDISCOVERY STM32 value line Discovery): STM32 discovery board description, schematics…
UM0985 (Developing your STM32VLDISCOVERY application using the IAR Embedded Workbench software): Tools description...
All docs are available from

85. Develop your application around STM32F100 device
Now you are able to…
Develop your application around STM32F100 device

86. Thank you