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MS_uC / fue1 / V01 5- 1 VIC - Vectored Interrupts Programming Microcontroller NVIC – Nested vectored interrupt controller Autumn term 2012.

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Presentation on theme: "MS_uC / fue1 / V01 5- 1 VIC - Vectored Interrupts Programming Microcontroller NVIC – Nested vectored interrupt controller Autumn term 2012."— Presentation transcript:

1 MS_uC / fue1 / V VIC - Vectored Interrupts Programming Microcontroller NVIC – Nested vectored interrupt controller Autumn term 2012

2 MS_uC / fue1 / V VIC - Vectored Interrupts Programming without interrupts  The main() function executes all peripheral calls in a fixed sequence

3 MS_uC / fue1 / V01 Programming with interrupts 5- 3 VIC - Vectored Interrupts

4 MS_uC / fue1 / V VIC - Vectored Interrupts Introduction z Exception are events yThey occur during the execution of the program z Type of ARM exceptions yExceptions that result by a command x Software- Interrupt x Undefined instruction xPre fetch Abort (memory access errors during the command reading) yExceptions that result as a side effect of a command xData Abort (memory access errors during the reading or writing of variables) yExternally generated exceptions (asynchrony) x Reset xHardware- Interrupts: IRQ

5 MS_uC / fue1 / V01 5 Program execution when an exception occurs

6 MS_uC / fue1 / V01 6 Properties of the exceptions zDifference between the ISR and the standard function calls y The standard function calls are realized in a synchronous manner with branch instructions y Interrupt service routines are called when an exception signals occur x Vector table contains the addresses of the interrupt service routines

7 MS_uC / fue1 / V01 7 Priorities of the exceptions zThe following questions must be answered for the case when several exceptions occur at the same time y Which exception should be treated at first? y Can an ISR be interrupted by an interruption signal? z The exceptions have different priorities in most microprocessors y Their priorities can even be fixed specifically by software in some cases

8 MS_uC / fue1 / V01 8 Priorities of the exceptions (Ref. Cortex-M3 Technical Reference Manual) zNVIC supports software-assigned priority levels yPriority level from 0 to 255 can be assigned to each hardware Interrupt  PRI_N field of the Interrupt Priority Register zAll priority levels can be split into a preemption and a sub priorities  PRIGROUP field of the Application Interrupt and Reset Control Register

9 MS_uC / fue1 / V01 9 Example zThe main program is interrupted by a hardware interrupt IRQ [3] (UART with preemption priority 3) z During the treatment of the first hardware interrupt another hardware interrupt occurs (timer IRQ with preemption priority 1) yISR_UART will be interrupted by the ISR_Timer

10 MS_uC / fue1 / V01 Interrupt and exception vectors zWhen an exception or an interrupt occurs yCPU interrupts the execution of the main program yCPU jumps to the vector address, which dependents on the exception type zBase address of the vector table is usually 0 z Cortes M3 contains both an interrupt and an exception vector tables VIC - Vectored Interrupts

11 MS_uC / fue1 / V VIC - Vectored Interrupts Exception vector table of the Cortex M3 (Ref. RM0008 Reference manual) Position priority Type of Priorty AcronymDescriptionAddress ---Reserved 0x0000_ fixedReset 0x0000_ fixedUMINon maskable interrupt 0x0000_0008 settableHardFaultAll class of fault 0x0000_000C 0settableMemManageMemory management 0x0000_0010 1settableBusFaultPre-fetch fault, memory access fault 0x0000_0014 2settableUsageFaultUndefined instruction or illegal state 0x0000_ Reserved 0x0000_001C 0x0000_002B 3settableSCCallSystem service call via SWI instruction 0x0000_002C 4settableDebug Monitor 0x0000_ Reserved 0x0000_0034 5settablePendSVPendable request for system service 0x0000_0038 6SettableSysTickSystem tick timer 0x0000_003C

12 MS_uC / fue1 / V01 Interrupt vector table of the Cortex M3 (1) VIC - Vectored Interrupts Positio n priority Type of Priorty AcronymDescriptionAddress 07settableWWDGWindow Watchdog interrupt 0x0000_ settablePVDPVD through EXTI Line detection interrupt 0x0000_ settableTAMPERTamper interrupt 0x0000_ settableRTCRTC global interrupt 0x0000_004C 411settableFLASHFlash global interrupt 0x0000_ settableRCCRCC global interrupt 0x0000_ settableEXTI0EXTI Line0 interrupt 0x0000_ settableEXTI1EXTI Line1 interrupt 0x0000_005C 815settableEXTI2EXTI Line2 interrupt 0x0000_ settableEXTI3EXTI Line3 interrupt 0x0000_ settableEXTI4EXTI Line4 interrupt 0x0000_ settableDMA1_Channel1DMA1 Channel1 global interrupt 0x0000_006C 1219settableDMA1_Channel2DMA1 Channel2 global interrupt 0x0000_ settableDMA1_Channel3DMA1 Channel3 global interrupt 0x0000_ settableDMA1_Channel4DMA1 Channel4 global interrupt 0x0000_ settableDMA1_Channel5DMA1 Channel5 global interrupt 0x0000_007C 16 23settableDMA1_Channel6DMA1 Channel6 global interrupt 0x0000_0080

13 MS_uC / fue1 / V01 Interrupt vector table of the Cortex M3 (2) VIC - Vectored Interrupts Position priority Type of Priorty AcronymDescriptionAddress 1724settableDMA1_Channel7DMA1 Channel7 global interrupt 0x0000_ settableADC1_2ADC1 and ADC2 global interrupt 0x0000_ settableCAN1_TXCAN1 TX interrupts 0x0000_008C 2027settableCAN1_RX0CAN1 RX0 interrupts 0x0000_ settableCAN1_RX1CAN1 RX1 interrupt 0x0000_ settableCAN1_SCECAN1 SCE interrupt 0x0000_ settableEXTI9_5EXTI Line[9:5] interrupts 0x0000_009C 2431settableTIM1_BRKTIM1 Break interrupt 0x0000_00A0 2532settableTIM1_UPTIM1 Update interrupt 0x0000_00A4 2633settableTIM1_TRG_COMTIM1 Trigger & Commutation interrupts 0x0000_00A8 2734settableTIM1_CC TIM1Capture Compare interrupt 0x0000_00AC 2835settableTIM2TIM2 global interrupt 0x0000_00B0 2936settableTIM3TIM3 global interrupt 0x0000_00B4 3037settableTIM4TIM4 global interrupt 0x0000_00B8 3138settableI2C1_EVI2C1 event interrupt 0x0000_00BC 3239settableI2C1_ERI2C1 error interrupt 0x0000_00C0

14 MS_uC / fue1 / V01 Interrupt vector table of the Cortex M3 (3) VIC - Vectored Interrupts Position priority Type of Priorty AcronymDescriptionAddress 3340settableI2C2_EVI2C2 event interrupt 0x0000_00C4 3441settableI2C2_ERI2C2 error interrupt 0x0000_00C8 3542settableSPI1SPI1 global interrupt 0x0000_00CC 3643settableSPI2SPI2 global interrupt 0x0000_00D0 3744settableUSART1USART1 global interrupt 0x0000_00D4 3845settableUSART2USART2 global interrupt 0x0000_00D8 3946settableUSART3USART3 global interrupt 0x0000_00DC 4047settableEXTI15_10EXTI Line[15:10] interrupts 0x0000_00E0 4148settableRTCAlarmRTC alarm through EXTI line interrupt 0x0000_00E4 4249settableOTG_FS_WKUPUSB On-The-Go FS Wakeup through EXTI line interrupt 0x0000_00E Reserved 0x0000_00EC 0x0000_ settableTIM5TIM5 global interrupt 0x0000_ settableSPI3SPI3 global interrupt 0x0000_010C 5259settableUART4UART4 global interrupt 0x0000_ settableUART5UART5 global interrupt 0x0000_0114

15 MS_uC / fue1 / V01 Interrupt vector table of the Cortex M3 (4) VIC - Vectored Interrupts Position priority Type of Priorty AcronymDescriptionAddress 5461settableTIM6TIM6 global interrupt 0x0000_ settableTIM7TIM7 global interrupt 0x0000_011C 5663settableDMA2_Channel1DMA2 Channel1 global interrupt 0x0000_ settableDMA2_Channel2DMA2 Channel2 global interrupt 0x0000_ settableDMA2_Channel3DMA2 Channel3 global interrupt 0x0000_ settableDMA2_Channel4DMA2 Channel4 global interrupt 0x0000_012C 6067settableDMA2_Channel5DMA2 Channel5 global interrupt 0x0000_ settableETHEthernet global interrupt 0x0000_ settableETH_WKUPEthernet Wakeup through EXTI line interrupt 0x0000_ settableCAN2_TXCAN2 TX interrupts 0x0000_013C 6471 settableCAN2_RX0CAN2 RX0 interrupts 0x0000_ settableCAN2_RX1CAN2 RX1 interrupt 0x0000_ settableCAN2_SCECAN2 SCE interrupt 0x0000_ settableOTG_FSUSB On The Go FS global interrupt 0x0000_014C

16 MS_uC / fue1 / V01 Masking of the Interrupts VIC - Vectored Interrupts zThe interrupts can be activated or deactivated zThe Nested Vectored Interrupt Controller (NVIC) realize this operation within the Cortex M3 processors

17 MS_uC / fue1 / V VIC - Vectored Interrupts Nested Vectored Interrupt Controller (NVIC) (Ref. RM0008 Reference manual) zFeatures y68 (not including the sixteen Cortex™-M3 interrupt lines) y16 programmable priority levels (4 bits of interrupt priority are used) yLow-latency exception and interrupt handling yPower management control yImplementation of System Control Registers zThe NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts zAll interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to STM32F10xxx Cortex-M3 programming manual ®

18 MS_uC / fue1 / V01 Bloc Schematic of the NVIC (Ref. Cortex-M3 Technical Reference manual) VIC - Vectored Interrupts

19 MS_uC / fue1 / V01 NVIC Register Overview (Ref. Cortex- M3 Technical Reference manual) VIC - Vectored Interrupts Name of the registerTypeAddress Interrupt Controller Type RegisterRead-only 0xE000_E004 SysTick Control and Status RegisterRead/write 0xE000_E010 SysTick Reload Value RegisterRead/write 0xE000_E014 SysTick Current Value RegisterRead/write clear 0xE000_E018 SysTick Calibration Value RegisterRead-only 0xE000_E01C Irq 0 to 239 Set Enable RegisterRead/write 0xE000_E100 0xE000_E11C Irq 0 to 239 Clear Enable RegisterRead/write 0xE000_E100 0xE000_E11C Irq 0 to 239 Set Pending RegisterRead/write 0xE000_E200 0xE000_E21C Irq 0 to 239 Active Bit RegisterRead-only 0xE000_E300 0xE000_E31C Irq 0 to 239 Priority RegisterRead/write 0xE000_E400 0xE000_E4F0

20 MS_uC / fue1 / V01 NVIC Register Descriptions zIRQ 0 to 239 Set-Enable Registers yEnable interrupts yDetermine which interrupts are currently enabled zIRQ 0 to 239 Clear-Enable Registers yDisable interrupts yDetermine which interrupts are currently disabled zIRQ 0 to 239 Set-Pending Register yForce interrupts into the pending state yDetermine which interrupts are currently pending zIRQ 0 to 239 Clear-Pending Register yClear pending interrupts yDetermine which interrupts are currently pending VIC - Vectored Interrupts

21 MS_uC / fue1 / V01 NVIC Priority Register descriptions zInterrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts VIC - Vectored Interrupts

22 MS_uC / fue1 / V VIC - Vectored Interrupts NVIC Configuration zActivation of an interrupt channel requires the following NVIC register configurations yEnable the interrupt channel by setting the its enable bit in the corresponding IRQ 0 to 239 Set-Enable Registers yFix the priority of the interrupt channel in its Interrupt Priority Register zCode example y/* Enable the EXTI9_5 Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); ®

23 MS_uC / fue1 / V VIC - Vectored Interrupts External interrupt/event controller (EXTI) zEXTI consists of up to 20 edge detectors for generating event/interrupt requests zFeatures yIndependent trigger and mask on each interrupt/event line yDedicated status bit for each interrupt line yGeneration of up to 20 software event/interrupt request yDetection of external signal with pulse width lower than APB2 clock ®

24 MS_uC / fue1 / V VIC - Vectored Interrupts EXTI Block diagram

25 MS_uC / fue1 / V VIC - Vectored Interrupts EXTI Configuration zTo configure the 20 lines as interrupt/event source  Configure the mask bits of the 20 Interrupt lines (EXTI_IMR  0x4001_04000 )  Configure the Trigger Selection bits of the Event lines (EXTI_RTSR  0x4001_0408 and EXTI_FTSR  0x4001_040C ) zCode example y/* Configure EXTI interrupt on PIN PB7 (User button) */ EXTI_InitStructure.EXTI_Line = EXTI_Line7; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure);

26 MS_uC / fue1 / V01 External Interrupt/Event GPIO mapping VIC - Vectored Interrupts

27 MS_uC / fue1 / V01 GPIO Configuration VIC - Vectored Interrupts  Select the port pin in the corresponding AFIO_EXTICRx register zCode example y/* Selects the pin PB7 as EXTI line */ GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource7);


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