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ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 11.

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Presentation on theme: "ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 11."— Presentation transcript:

1 ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 11

2 Topics Interrupt Concepts ARM7TDMI Interrupt Handling ADuC7026 Interrupt Implementation Interrupt Sources Interrupt Service Routines (ISRs) Interrupt Driven Systems Software Interrupts and Exceptions Interrupt Priority and Latency Debugging Interrupt Hardware and Software

3 Why Use Interrupts? Maximize processor utilization and efficiency Allow use of sleep/idle states to save power Minimize latency in responding to complex input/output structures Facilitate event-driven applications and preemptive multitasking

4 Interrupt Primer Terminology Basic interrupt hardware Interrupt request Interrupt acknowledge Interrupt masking  Non-maskable interrupt (NMI) Interrupt sensitivity  Level-sensitive  Edge-sensitive

5 Interrupt Concepts Supporting multiple interrupt sources Polled interrupts Vectored interrupts  Fixed ISR locations  Vector table implementations Generic implementation Prioritization Schemes Fixed Rotating Hierarchical Software interrupts and exceptions

6 ARM7TDMI Interrupt Handling Interrupt modes IRQ  Banks R13, R14, SPSR BanksSPSR FIQ  Banks R8-R12, R13, R14, SPSR BanksSPSR SWI (software interrupt) discussed later Interrupt control  CPSR I/F flags CPSR Interrupt processing sequence Interrupt nesting

7 ADuC7026 Hardware Interrupts Interrupt sources Internal peripherals External IRQ pins Programmed interrupts Interrupt sources can be individually programmed to generate either FIQ or IRQ mode entry. No prioritization of individual sources at a given level (FIQ/IRQ)

8 ADuC7026 Interrupt MMRs These MMRs are used to control the interrupt handling IRQSIG, FIQSIG  Ones indicate that the source has an interrupt pending IRQEN, FIQEN  Ones indicate that the interrupt request from the source is unmasked (i.e. the interrupt source is enabled) IRQSTA, FIQSTA  Ones indicate that the sources have an interrupt enabled and pending  Used in ISR to determine which device(s) need(s) service IRQCLR, FIQCLR  Write ones to clear the corresponding bit in IRQEN, FIQEN (i.e. to mask an interrupt source)  This is NOT how you clear an interrupt request in the ISR!

9 ADuC7026 Programmed Interrupts The programmed interrupt feature allows us to programmatically force an entry into FIQ mode or IRQ mode Write to SWICFG register, do not need to have programmed interrupt enabled in IRQEN/FIQEN Note that the use of “SWI” has absolutely nothing to do with the ARM7 SWI instruction and supervisor mode

10 Interrupt Service Routines ISR prerequisites aduc7026.s ISR implementation Context save Clear IRQ from interrupt source Allow nesting (if desired) Handle interrupt Context restore Return from interrupt/exception Interrupt ChecklistInterrupt Checklist on course web page Shared subroutines and resources

11 Interrupt Driven Systems Foreground vs. background tasks. Events determine the actual order of execution.

12 Software Interrupts & Exceptions SWI instruction Exceptions ARM7TDMI exceptions  Prefetch abort  Data abort  Undefined instruction  Reset Other common exceptions  Divide error  Single-step  Breakpoint

13 Interrupt Prioritization and Latency Handling multiple simultaneous interrupts and exceptions ARM7TDMI exception priorities Interrupt prioritization schemes  Fixed  Rotating  Tiered (hierarchical) Interrupt Latency Definition ADuC7026 latency specifics

14 Interrupt Issues Using periodic interrupts to perform iterative tasks What to do when good interrupts go bad… Software debugging Hardware debugging Real-time issues Inter-process communication (IPC) issues

15 In-Class Assessment Quiz What sort of safeguards might you need to design into NMI hardware? For the ARM7TDMI, describe what happens between an IRQ being asserted and the actual execution of the ISR. What are the differences between vectored interrupts and polled interrupts?

16 In-Class Assessment Quiz What is a ‘level-sensitive’ interrupt? What problems could arise when using a semaphore to control access to a resource used by the main program and an ISR? What ARM7TDMI instruction(s) help handle this issue? Draw a flowchart for a periodic (1 KHz) ISR that will be used to generate precise millisecond delays. Only a single word variable is to be used to communicate with the ISR.

17 Wrapping Up Homework #6 due Wednesday, 4/25. Reading for next week Textbook 15 Supplement #5

18 ARM7 CPSR Current Process Status Register (CPSR) Condition code flags (N, Z, C, V) Interrupt disable bits (I, F) Thumb mode enable (T)  Never change directly! Mode select  These bits cannot be changed in User mode NZCVreservedIFTmode

19 ARM7 SPSR Suspended Process Status Register (SPSR) SPSR is only present when the CPU is operating in one of the exception modes  Each exception mode has its own SPSR, since exception handlers may cause other exceptions. SPSR is a copy of the CPSR immediately before the exception mode was entered.  When returning from the exception, the value in SPSR is used to restore the CPSR to the proper state for the process that was interrupted.

20 ARM7 Register Banking User Mode Privileged Modes Exception Modes UserSystemSupervisorAbortUndefinedIRQFIQ R0-R7 R8-R12 R13-R14 PC CPSR SPSR

21 Interrupt Example - Hardware

22 aduc7026.s AREA Reset, CODE, READONLY ARM ; Exception Vectors mapped to Address 0. ; Absolute addressing mode must be used. Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector LDR PC, IRQ_Addr LDR PC, FIQ_Addr Reset_Addr DCD Reset_Handler Undef_Addr DCD Undef_Handler SWI_Addr DCD SWI_Handler PAbt_Addr DCD PAbt_Handler DAbt_Addr DCD DAbt_Handler IRQ_Addr DCD IRQ_Handler FIQ_Addr DCD FIQ_Handler Reset_Handler ;setup PLL and power control LDR R1, =PLL_MMR_BASE

23 aduc7026.s LDR R0, =Stack_Top ; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size... ; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size ; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size ; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size ; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR MOV SP, R0 SUB SL, SP, #USR_Stack_Size ; jump to user code B __main

24 ADuC7026 Interrupt Latency

25 ADuC7026 Exception Priority


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