Presentation on theme: "ECE 353 Introduction to Microprocessor Systems"— Presentation transcript:
1ECE 353 Introduction to Microprocessor Systems Week 11Michael G. Morrow, P.E.
2Topics Interrupt Concepts ARM7TDMI Interrupt Handling ADuC7026 Interrupt ImplementationInterrupt SourcesInterrupt Service Routines (ISRs)Interrupt Driven SystemsSoftware Interrupts and ExceptionsInterrupt Priority and LatencyDebugging Interrupt Hardware and Software
3Why Use Interrupts? Maximize processor utilization and efficiency Allow use of sleep/idle states to save powerMinimize latency in responding to complex input/output structuresFacilitate event-driven applications and preemptive multitasking
7ADuC7026 Hardware Interrupts Interrupt sourcesInternal peripheralsExternal IRQ pinsProgrammed interruptsInterrupt sources can be individually programmed to generate either FIQ or IRQ mode entry.No prioritization of individual sources at a given level (FIQ/IRQ)
8ADuC7026 Interrupt MMRsThese MMRs are used to control the interrupt handlingIRQSIG, FIQSIGOnes indicate that the source has an interrupt pendingIRQEN, FIQENOnes indicate that the interrupt request from the source is unmasked (i.e. the interrupt source is enabled)IRQSTA, FIQSTAOnes indicate that the sources have an interrupt enabled and pendingUsed in ISR to determine which device(s) need(s) serviceIRQCLR, FIQCLRWrite ones to clear the corresponding bit in IRQEN, FIQEN (i.e. to mask an interrupt source)This is NOT how you clear an interrupt request in the ISR!
9ADuC7026 Programmed Interrupts The programmed interrupt feature allows us to programmatically force an entry into FIQ mode or IRQ modeWrite to SWICFG register, do not need to have programmed interrupt enabled in IRQEN/FIQENNote that the use of “SWI” has absolutely nothing to do with the ARM7 SWI instruction and supervisor mode
10Interrupt Service Routines ISR prerequisitesaduc7026.sISR implementationContext saveClear IRQ from interrupt sourceAllow nesting (if desired)Handle interruptContext restoreReturn from interrupt/exceptionInterrupt Checklist on course web pageShared subroutines and resources
11Interrupt Driven Systems Foreground vs. background tasks.Events determine the actual order of execution.
13Interrupt Prioritization and Latency Handling multiple simultaneous interrupts and exceptionsARM7TDMI exception prioritiesInterrupt prioritization schemesFixedRotatingTiered (hierarchical)Interrupt LatencyDefinitionADuC7026 latency specifics
14Interrupt Issues Using periodic interrupts to perform iterative tasks What to do when good interrupts go bad…Software debuggingHardware debuggingReal-time issuesInter-process communication (IPC) issues
15In-Class Assessment Quiz What sort of safeguards might you need to design into NMI hardware?For the ARM7TDMI, describe what happens between an IRQ being asserted and the actual execution of the ISR.What are the differences between vectored interrupts and polled interrupts?
16In-Class Assessment Quiz What is a ‘level-sensitive’ interrupt?What problems could arise when using a semaphore to control access to a resource used by the main program and an ISR? What ARM7TDMI instruction(s) help handle this issue?Draw a flowchart for a periodic (1 KHz) ISR that will be used to generate precise millisecond delays. Only a single word variable is to be used to communicate with the ISR.
17Wrapping Up Homework #6 due Wednesday, 4/25. Reading for next week Textbook 15Supplement #5
18ARM7 CPSR Current Process Status Register (CPSR) Condition code flags (N, Z, C, V)Interrupt disable bits (I, F)Thumb mode enable (T)Never change directly!Mode selectThese bits cannot be changed in User mode31302928272625242322212019181716151413121110987654321NZCVreservedIFTmode
19ARM7 SPSR Suspended Process Status Register (SPSR) SPSR is only present when the CPU is operating in one of the exception modesEach exception mode has its own SPSR, since exception handlers may cause other exceptions.SPSR is a copy of the CPSR immediately before the exception mode was entered.When returning from the exception, the value in SPSR is used to restore the CPSR to the proper state for the process that was interrupted.
22aduc7026.s AREA Reset, CODE, READONLY ARM ; Exception Vectors mapped to Address 0.; Absolute addressing mode must be used.VectorsLDR PC, Reset_AddrLDR PC, Undef_AddrLDR PC, SWI_AddrLDR PC, PAbt_AddrLDR PC, DAbt_AddrNOP ; Reserved VectorLDR PC, IRQ_AddrLDR PC, FIQ_AddrReset_Addr DCD Reset_HandlerUndef_Addr DCD Undef_HandlerSWI_Addr DCD SWI_HandlerPAbt_Addr DCD PAbt_HandlerDAbt_Addr DCD DAbt_HandlerIRQ_Addr DCD IRQ_HandlerFIQ_Addr DCD FIQ_HandlerReset_Handler;setup PLL and power controlLDR R1, =PLL_MMR_BASE
23aduc7026.sLDR R0, =Stack_Top; Enter Undefined Instruction Mode and set its Stack PointerMSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_BitMOV SP, R0SUB R0, R0, #UND_Stack_Size...; Enter FIQ Mode and set its Stack PointerMSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_BitSUB R0, R0, #FIQ_Stack_Size; Enter IRQ Mode and set its Stack PointerMSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_BitSUB R0, R0, #IRQ_Stack_Size; Enter Supervisor Mode and set its Stack PointerMSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_BitSUB R0, R0, #SVC_Stack_Size; Enter User Mode and set its Stack PointerMSR CPSR_c, #Mode_USRSUB SL, SP, #USR_Stack_Size; jump to user codeB __main