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PROGRAMMING LANGUAGE CREATION FOR CONTROLING INTERNAL TRANSPORT DEVICES Józef Okulewicz Warsaw University of Technology, Faculty of Transport Telematyka, 2007

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www.oreilly.com HISTORY OF PROGRAMMING LANGUAGES 2004 FORTRAN X 1954

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Eric Levenez, July 2007 http://www.levenez.com/lang/history.html FORTRAN X 1954 2006

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John Backus is the father of Fortran, the language that froze computer architectures to this day. But he wrote in 1981: „While it is perhaps natural and inevitable that languages like Fortran and its successors should have developed out of the concept of the von Neumann computer as they did, the fact that such languages have dominated our thinking for twenty years is unfortunate. … because their long-standing familiarity will make it hard for us to understand and adopt new programming styles which one day will offer far greater intellectual and computational power.” Richard P. Gabriel, Guy L. Steele Jr. : What Computers Can’t Do (And Why), Lisp and Symbolic Computation (LASC), vol. 1, n. 3-4. 1986

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A Boolean algebra is also called a Boolean lattice. The connection to lattices (special partially ordered sets) is suggested by the parallel between set inclusion, A ⊆ B, and ordering, a ≤ b. Consider the lattice of all subsets of {x,y,z}, ordered by set inclusion. This Boolean lattice is a partially ordered set in which, say, {x} ≤ {x,y}. Any two lattice elements, say p = {x,y} and q = {y,z}, have a least upper bound, here {x,y,z}, and a greatest lower bound, here {y}. Suggestively, the least upper bound (or join or supremum) is denoted by the same symbol as logical OR, p ∨ q; and the greatest lower bound (or meet or infimum) is denoted by same symbol as logical AND, p ∧ q.latticespartially ordered setsinclusionordering WIKIPEDIA http://en.wikipedia.org/wiki/

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spacetime accessibility SYSTEM NOTIONS STRUCTURE 1001 11 LOGICAL LATICE OF 2 VARIABLES

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100 001 010 101 110 011 111 LOGICAL LATICE OF 3 VARIABLES

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space aim time transparency accessibility connectivity integrity SYSTEM NOTIONS STRUCTURE

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v* q* ::= transparency accessibility connectivity @#@# ” for ” # nil ” if ” nil + @ ” go ”

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STRUCTURE OF THE TRANSPORT SYSTEM program instructions objects generating priority object conveyor segment segment controling

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@w1 @w2 @w3 @t5 @t6 @s1 @s2 @s3 @C @t7 @z1 @z2 @z3 @b3 @* ► @A v2 #z1 @A v1 #z1 +20 :A @B #z1 @t1 v2 #z1 :t5 @t4 v1 #z1 @t5 v2 #z1 @B #z1 @B v2 #z1 @B v1 #z1 +20 :B @t1 v1 #z1 @t2 v2 #z1 @t2 v1 #z1 +50 #w1 #z1/0.1;z2/0.4;z3 +R(40,120) #w2 #z1/0.1;z2/0.5;z3 +R(60,140) #w3 #z1/0.1;z2/0.6;z3 +E(100) PROGRAM LINEAR STRUCTURE :s1 @t5 v1 #z1 @s1 v2 #z1 @s1 v1 #z1 +10 @s1 #z1 @s1 #z2 @s1 #z3 @s2 #z2 @s2 #z3 @s3 #z3 @C v2 #z1 @C v1 #z1 +20 :C @B #z1 @t3 v2 #z1 @z1 v2 #z1 @z1 v1 #z1 +10 @t4 v2 #z1 @t3 v1 #z1

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w1 @w1 #w1 #z1/0.1;z2/0.4;z3 +R(40,120) s1 @s1 @t5 v1 #z1 @s1 v2 #z1 @s1 v1 #z1 +10 @s1 #z1 @s1 #z2 @s1 #z3 z1 @z1 @z1 v2 #z1 @z1 v1 #z1 +10 w2 @w2 #w2 #z1/0.1;z2/0.5;z3 +R(60,140) s2 @s2 @s2 #z2 @s2 #z3 z2 @z2 w3 @w3 #w3 #z1/0.1;z2/0.6;z3 +E(100) s3 @s3 @s3 #z3 z3 @z3 A @A v2 #z1 @A v1 #z1 +20 @B #z1 B @B #z1 @B v2 #z1 @B v1 #z1 +20 @t1 v1 #z1 C @C @C v2 #z1 @C v1 #z1 +20 @B #z1 b3 @b3 t1 @t1 v2 #z1 t2 @t2 v2 #z1 @t2 v1 #z1 +50 t3 @t3 v2 #z1 t4 @t4 v2 #z1 @t3 v1 #z1 t5 @t5 @t4 v1 #z1 @t5 v2 #z1 t6 @t6 t7 @t7 central @* ► INSTRUCTION ASSIGNMENT TO CONVEYOR SECTIONS

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Linear Algebra. Circuits The circuits in computers and other input devices have inputs, each of which is either a 0 or 1, the output is also 0s and 1s.

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