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Quick Start to VHDL VHDL Very Hard Difficult Language Very Hard Difficult Language!!!!!!!

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Presentation on theme: "Quick Start to VHDL VHDL Very Hard Difficult Language Very Hard Difficult Language!!!!!!!"— Presentation transcript:

1 Quick Start to VHDL VHDL Very Hard Difficult Language Very Hard Difficult Language!!!!!!!

2 Quick Start to VHDL VHDL V ery High Speed Integrated Circuits V ery High Speed Integrated Circuits H ardware D escription L anguage

3 How You can do VHDL 1.Behavior Method Specify the relationship between inputs and output Y<= (A XOR B) OR C 2. Structural Method Mapping between logical components

4 VHDL Fundamentals –Libraries and Packages –Entity (Data Types) –Architecture –Signals (Data Types) –Operators

5 Libraries and Packages  Libraries provide a set components and functions that simplify the task of designing  Packages provide subprograms maybe used in a design  The following is an example of the use of the IEEE library and its STD_LOGIC_1164 package: LIBRARY ieee; USE ieee.std_logic_1164.ALL;

6 Entities  An entity is a specification of the design’s external interface  Entity declarations specify the following: 1.Name of the entity 2.Set of port declarations defining the inputs and outputs to the hardware design  The following is an example of an entity declaration: ENTITY orgate IS PORT ( a : INSTD_LOGIC; b : INSTD_LOGIC; y : OUTSTD_LOGIC ); END orgate; Port Direction Port Data Type

7 Ports  Port name choices: –Always begin with a letter –Case insensitive  Port direction choices: IN Input port OUT Output port  Port signal type (suggested) choices: –STD_LOGIC –STD_LOGIC_VECTOR( DOWNTO ) for 8bit data type : std_logic_vector(7 downto 0) –Integer –Real –Boolean

8 Architectures  An architecture is a specification of the design’s internal implementation  The following is an example of an architecture declaration: ARCHITECTURE a OF orgate IS BEGIN y <= a or b; END a;

9 Logical Operators  VHDL supports the following logical operators:  AND  OR  XOR  XNOR  NOT  NAND  NOR

10 Other Operators  VHDL supports the following relational operators: = (Equal) /= (Not Equal) <(Less Than) >(Greater Than)  VHDL supports the following mathematical operators: +(Addition) -(Subtraction) *(Multiplication) /(Division) Abs(Absolute) **(Exponentiation)

11 Complete Example LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY orgate IS PORT ( a : INSTD_LOGIC; b : INSTD_LOGIC; y : OUTSTD_LOGIC ); END orgate; ARCHITECTURE a OF orgate IS BEGIN y <= a or b; END a;

12 Start With MaxPlus II  Software is used to check, compile and simulate the VHDL code.  start MAX+PLUS II

13  Select File  New.  Select Text Editor File. Start With MaxPlus II

14  In the new empty window write the VHDL input file. LIBRARY ieee; USE ieee.std_logic_1164.ALL ENTITY orgate IS PORT ( a : INSTD_LOGIC; b : INSTD_LOGIC; c : OUTSTD_LOGIC ); END orgate; ARCHITECTURE a OF orgate IS BEGIN c <= a or b; END a; Start With MaxPlus II

15  Save the File as Vhd,Select File  Save As. Save using the same name of the entity Start With MaxPlus II

16  Set project to Current File,Select File Project  Set Project to Current File. Start With MaxPlus II

17  Compile by selecting File  Project  Save and Compile. A window with the modular compiler, will monitor compiling, warnings and errors. errors. Start With MaxPlus II

18  For simulation:  Choose File  New, select Waveform Editor File, and then click OK  Select Node  Enter Node from SNF  Click on List to list the input & output ports  Select these ports Start With MaxPlus II

19  Modify the inputs  Select File  Project  Save and Simulate Start With MaxPlus II

20 library ieee; use ieee.std_logic_1164.all; --full_adder entity full_adder is port ( a,b,cin: in std_logic; sum,cout:out std_logic); end full_adder; architecture full_adderfun of full_adder is signal sum1, c1, c2:std_logic; begin sum1 <= a xor b; sum <= sum1 xor cin; c1 <= sum1 and cin; c2 <= a and b; cout <= c1 or c2; end full_adderfun; 2 nd Complete Example

21 Signals  Signals represent wires and storage elements within a VHDL design  Signals only be defined inside architectures  Signals are associated with a data type

22 UP2 Education Board The board contains: FLEX® 10K FPGA deviceFLEX® 10K FPGA device MAX® 7000 PLDMAX® 7000 PLD One OscillatorOne Oscillator Four JumpersFour Jumpers Four Push ButtonFour Push Button 16 LED’S16 LED’S Four Seven Segment DisplaysFour Seven Segment Displays Three SwitchesThree Switches Four ExpansionsFour Expansions

23 UP2 Education Board FLEX® 10K FPGA Contains 70,000 gates, 3744 logic elements, 4096 register and RAM bits.Contains 70,000 gates, 3744 logic elements, 4096 register and RAM bits. Connections are made using pass-transistors, transmission gates, or multiplexersConnections are made using pass-transistors, transmission gates, or multiplexers Fast in-circuit reconfigurationFast in-circuit reconfiguration Volatile memory chipVolatile memory chip

24 UP2 Education Board MAX® 7000 PLD EPROM (Erasable Programmable) TechnologyEPROM (Erasable Programmable) Technology Non-volatile memory chipNon-volatile memory chip Capacity of 2,500 gates and 128 macro cellsCapacity of 2,500 gates and 128 macro cells Each macro cell has a programmable-AND/fixed-OR array as well as a configurable registerEach macro cell has a programmable-AND/fixed-OR array as well as a configurable register

25 UP2 Education Board Oscillator  The UP Education Board contains a MHz crystal oscillator.  The output of the oscillator drives a clock input to the EPM7128S device (pin 83) FLEX 10K device (pin 91)

26 UP2 Education Board Jumpers  The UP Education Board has four three-pin jumpers (TDI, TDO, DEVICE, and BOARD)   The jumpers setting to configure: FLEX 10KEPM7128S

27 UP2 Education Board Push Buttons  Four push buttons: Two are connected to EPM7128S (MAX_PB1 & MAX_PB2 ) and two are connected to FLEX 10K (FLEX_PB1 & FLEX_PB2 )  Each push button is pulled-up to 5 V through a 10-KΩ resistor. (Active Low when pressed)  MAX_PB1 & MAX_PB2 can be connected to any input of the device expansion.  FLEX_PB1 connected to pin 28, and FLEX_PB2 connected to pin 29.

28 UP2 Education Board LED’s  Contains 16 LEDs that are pulled-up with a 330- Ω resistor.  An LED is illuminated when a logic 0 is applied to the female header associated with the LED

29 UP2 Education Board 7 Segment Display  Four 7 Segment Displays: Two are connected to EPM7128S and two to FLEX 10K  Each LED segment of the display can be illuminated by driving the connected pin with a logic 0

30 UP2 Education Board 7 Segment Display FLEX 10K EPM7128S

31 UP2 Education Board Switches  Three 8 switches: Two are connected to EPM7128S (MAX_SW1 & MAX_SW2 Switches) and one to FLEX 10K (FLEX_SW1 Switches)  An input pin is set to logic 1 when the switch is open and set to logic 0 when the switch is closed.  MAX_SW1 & MAX_SW2 Switches can be connected to any input of the device expansion  FLEX_SW1 Switches are connected as following:

32 UP2 Education Board Switches

33 UP2 Education Board Expansions  MAX_EXPANSION FLEX_EXPAN_A, FLEX_EXPAN_B, and FLEX_EXPAN_C are dual rows of 0.1-inch spaced holes for accessing signal I/O pins

34 UP2 Education Board Expansions

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38  Select Assign  Device  To assign the chip that will be used to configure the design. Here FLEX10K is assigned with the chip number EPF10K70RC240-2 that is written on the chip. Programming With MaxPlus II

39  Select Assign  Pin/Location/Chip Programming With MaxPlus II Click Search Click List

40 Programming With MaxPlus II Pin 28 is Flex_PB1 Pin 29 is Flex_PB2 Pin 41 is Flex switch1 Pin 6 is (a) of 7seg1 Pin 17 is (a) of 7seg2

41 Programming With MaxPlus II  Select Mxx+Pluss II  Programmer  Select JTAG  Multi-device JTAG chain so that a checkmark appears to the left of the option.  Hit the Select programming File button and select full_adder.sof.  Click OK, then click the ADD button and the new filename should move into the list in the inner window.  Select the Detect JTAG Chain Info button. The system should respond with “JTAG chain information confirmed by hardware check”.  If not, double check cables, power, jumpers, and make sure you have the correct file name and chip listed in the inner window.  Click OK to exit the JTAG Multi-device Setup window.

42  The configure button in the programming window should now be highlighted.  Click on the configure button to download to the board.  Just a few seconds are required to download. If download is successful, a window with Configuration Complete is displayed - click OK.  If the configure button is not highlighted, try Option  Hardware Setup from the pull-down window. confirm the port settings and click OK. Also confirm that the JTAG setup dialog information is correct. If you still have problems confirm that the printer port BIOS settings ESP or EPP mode. Programming With MaxPlus II


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