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Fast Electronics of T0 Detector 10 December 2004.

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Presentation on theme: "Fast Electronics of T0 Detector 10 December 2004."— Presentation transcript:

1 Fast Electronics of T0 Detector 10 December 2004

2 A. Klimov RRC KI Moscow 2 Placement of T0 fast electronics The electronic equipment (fast electronics) is assumed to be placed in VME crates and located in experimental area at the outer side of the L3 magnet.

3 A. Klimov RRC KI Moscow 3 Electronics equipment carries out three basic functions:  Realization of the logic selection allowing considerably to lower a level of background events at development of trigger signals TO;  Generation of signals, with precision accuracy fixing time marks of occurrence of pulses;  Measurement of the amplitude and time distributions of the signals of the detectors.

4 A. Klimov RRC KI Moscow 4 The overall diagram of T0 fast electronics Output pulses of multiplicity discriminators, circuits of coincidence (OR) and the block of time discrimination (TVDC) through NRZ module are transferred in CTP (Central Trigger Processor). Signals from shoeboxes go to analog splitters and further to QTC, CFD– discriminators and multiplicity discriminators. The output pulses of the CFD – discriminators through lines of a delay go to 12 channel circuits of coincidences (OR) for generation of signals TO-A, TO-C. Output pulses of QTC and CFD – discriminators go to TRM (TDC Readout Module) for conversion and the subsequent transfer in DAQ (Detector Acquisition System).

5 A. Klimov RRC KI Moscow 5 T0 Vertex Unit (TVDC) TVDC should meet the following requirements:  range of conversion time intervals:  2,5 ns(5 ns);  quantization step: 20 ps (for 8-bit conversion);  dead time of conversion: not more than 25 ns. The given parameters obtained with the use of time- amplitude converter and flash ADC with the digital discriminator for TO-vertex signal generation. TVDC is in CAMAC standard

6 A. Klimov RRC KI Moscow 6 Threshold characteristic of TVDC The duration of delay slope is determined by the real resolution (FWHM) of the detectors used in the experiment Measured at the CERN accelerator PMT position 1 PMT position 2 (shift = 18 cm)

7 A. Klimov RRC KI Moscow 7 TVDC calibration tests TVDC calibration spectrum  Calibration spectrum derived from the 0.5 ns discrete change of delay between start and stop pulse  Peak distance is 23 channels  The time resolution of TVDC is around 22 ps

8 A. Klimov RRC KI Moscow 8 Multiplicity Discriminator (MPD)  Number of inputs: 12  Maximum amplitude of the signal at each input: 3 V.  Minimal duration: 5 ns.  Rise time: 2.5 ns  The output signal at the Out1-Out3 outputs is in the NIM standard with the 10 ns duration MPD generates three logical signals corresponding to three levels of multiplicity:  Low ( minimum bias )  Intermediate (semi–central)  High (central) The multiplicity level is adjusted discretely (8-bit) Parameters: Pulse shape of the anode of the PMT MPD is in CAMAC standard

9 A. Klimov RRC KI Moscow 9 MPD linearity tests QDC doesn’t start analyze incoming amplitude signals until MPD produce ‘Strobe’ signal Emulation of multiplicity of PMT output signals

10 A. Klimov RRC KI Moscow 10 Other units (CFD, Mean Timer, Delay Unit, Logical Unit etc.) have prototypes but need further development and tuning. All electronics units was made in CAMAC standard. It is necessary to develop this units in VME standard.

11 A. Klimov RRC KI Moscow 11 It suggested to place FE units on 6U VME boards and use universal VME decoder. VME interface VME Board Functional part of CAMAC units

12 A. Klimov RRC KI Moscow 12 FPGA XILINX XC9500 Features  High-performance  5 ns pin-to-pin logic delays on all pins  f CNT to 125 MHz  Endurance of 10,000 program/erase cycles  Global and product term clocks, output enables, set and reset signals  Extensive IEEE Std boundary-scan (JTAG) support  High-drive 24 mA outputs  3.3V or 5V I/O capability  Advanced CMOS 5V Fast FLASH™ technology  Supports parallel programming of multiple XC9500 devices

13 A. Klimov RRC KI Moscow 13 Wiener VME 5021 Crate 19" VME bins:  8U or 9U bin for 6U x 160mm VME cards  21 slots  2U space for fan tray  Various backplanes possible: standard J1/J2, CERN-V430 J1/J2/Jaux, VME 64  Equipped with multiple high current connector board

14 A. Klimov RRC KI Moscow 14 VME Power Supply UEP 5021 Power Supply+5V+/-12V-2V-5.2V+/-15V+3.3VBackplane UEP 5021 / 11100A40A / 40A----standard J1/J2 UEP 5021 / 12200A40A / 40A----standard J1/J2 UEP 5021/ 13300A40A / 40A----standard J1/J2 UEP 5021 / 14400A40A / 40A----standard J1/J2 UEP 5021 / 55100A40A / 40A100A --V430 J1/J2/Jaux UEP 5021 / 60200A40A / 40A100A200A--V430 J1/J2/Jaux UEP 5021 / 65100A40A / 40A100A 30A / 30A-V430 J1/J2/Jaux UEP 5021 / 70200A40A / 40A100A200A30A / 30A-V430 J1/J2/Jaux UEP 5021 / 75100A40A / 40A100A 30A / 30A100Auser defined  Mains filter  Softstart circuit  Auxiliary power supply  Regulator-monitoring- and alarm-circuit supported by a self calibrating microprocessor system.

15 A. Klimov RRC KI Moscow 15 FE modules arrangement 6 Delays (4-ch. each) 2 ORs 2 MPDs 1 TVDC 6 QTCs (4-ch. each) 6 FAN-OUTs (4-ch. each) 12 CFDs (2 -ch. each) 1 TM 1 NRZ Module 17 modules20 modules Controlled by V2718 Without control 2 VME crates

16 A. Klimov RRC KI Moscow 16 Problems It is necessary to: develop prototype of QTC and NRZ module develop system of time synchronization (BC) for FE units develop system of laser calibration for detector T0 choose appropriate CFD for precision time measurement make uniform interfaces of DAQ and DCS

17 A. Klimov RRC KI Moscow 17 Power Supply of the TO Detector

18 A. Klimov RRC KI Moscow 18 Power Supply SY2527 (Mainframe) Remote control (Ethernet) Local control (keyboard)

19 A. Klimov RRC KI Moscow 19 Functional parts of the SY2527 Packaging - 19"-wide, 4U-high Euro- mechanics rack; - Depth: 770 mm. Weight Mainframe (*): 19 kg Power Requirements Voltage range: V Frequency: Hz Power: 1700 W Max. number of boards per crate 6 Power supply unit output +/-12 V, 8 A +5 V, 20 A +48 V, 15.6 A Max. output power 750 W Operating temperature From 5°C (dry atmosphere) to +40°C Storage temperature From -20°C (dry atmosphere) to +50°C Technical specifications

20 A. Klimov RRC KI Moscow 20 CAEN SY 2725 backplane 2 HV boards CAEN A 1733 is enough to obtain 24 HV outputs for PMTs

21 A. Klimov RRC KI Moscow 21 A1733 Power Supply Board PolarityPositive / Negative Output Voltage0 ÷ 4 kV Max. Output Current2/3 mA Voltage Set/Monitor Resolution250 mV Current Set/Monitor Resolution200 nA VMAX hardware0 ÷ 4 kV VMAX hardware accuracy± 2% of FSR VMAX software0 ÷ 4 kV VMAX software resolution1 V Voltage Ripple< 30 mV pp Voltage Set vs. Output Voltage Accuracy± 0.3% ± 0.25 V Current Monitor vs. Output Current Accuracy ± 2% ± 1 µA Current Set vs. Current Monitor Accuracy± 2% ± 0.2 µA

22 A. Klimov RRC KI Moscow 22 VME crate controller selection V2718+A2818: PCI – VME Bridge  VME64x compliant  Optical Link 1.25 Gbit/s  Daisy Chain Capability (up to 8 V2718 per 1 A2818)  PCI 32 bit / 33MHz  Low Protocol Overhead  Transfer rate: up to ~60 Mbyte/sec  No boot required: ready at power-up!  Front panel dataway display

23 A. Klimov RRC KI Moscow 23 PC SideCrate Side VME crate – PC connectivity PCI card A2818 allows to use 2 crate-controllers V2718 simultaneously

24 A. Klimov RRC KI Moscow 24 V2718 Software An user friendly interface has been developed by CAEN for the module’s control. This simple application can be used for adjusting and controlling VME devices. But in order to produce spectra and different distributions, or perform some unique tests for specific devices we need to develop own software. CAEN supply developers with library of functions which permits an user program to use and configure V2718.

25 A. Klimov RRC KI Moscow 25 TVDC trigger efficiency The 4 curves illustrate trigger efficiency as a function of vertex position recalculated for 4 different settings of the upper and lower threshold.

26 A. Klimov RRC KI Moscow 26 TVDC conversion linearity Integral non-linearity not more then  1,5%.

27 A. Klimov RRC KI Moscow 27 Constant Fraction Discriminator (CFD) Functional diagram of INR double input discriminator

28 A. Klimov RRC KI Moscow 28 Constant Fraction Discriminator (CFD) The arbitrary delay of the output signal of the CFD as a function of input amplitude taken from a PMT. In dynamic range of the input signals equal to 4 mV – 3 V the deviation of output signals delay does not exceed ±25 ps

29 A. Klimov RRC KI Moscow 29 Time Meaner  Input signals are in NIM standards of 10 ns duration;  Output signals are in NIM and LVDS standards;  Jitter of the output signal is not more then 20 ps;  The accuracy of timing (time binding to the middle point of time interval ranging within 3 ns) is not more then 20 ps.

30 A. Klimov RRC KI Moscow 30 Time Meaner Center of gravity on the time axis of two signals T0 A and T0 C in case of a fixed distance between two arrays of detectors (T0 A + T0 C )/2 is independent of the position of the vertex Principle of operation

31 A. Klimov RRC KI Moscow 31 Time Meaner Left wing – delay in input 1 Right wing – delay in input 2 This curve was measured by changing the delays of an input signal at the input 1 or at the input 2. It is clearly seen that the delay of the output signal is two times less than a delay of an input signal. The dynamic range of the device equal to ±5ns corresponds to the distance of the C- array from the nominal position of the vertex. The intrinsic jitter of the time meaner does not exceed 20 ps. Some non-linearity of the right wing of the characteristic of the device will be improved in a new prototype.

32 A. Klimov RRC KI Moscow 32 Logical Unit (OR) The logic unit is intended for generation of common signal TOA (or TOC) using the signal from 12 CFD units (constant fraction discriminators). Moreover, the logic unit provides the possibility for precise tuning of delays in each PMT-CFD channel by remote commutation of channels. The time gating can be also provided with the use of CLC (LHC) or BC signal.  Input signals are in NIM standard with the 10 ns duration;  Output signals are in NIM and LVDS (1 output) standards;  Jitter of the output signal is not more then 25 ps;  The unit is controlled by the 12-bit code. Parameters:

33 A. Klimov RRC KI Moscow 33 Variable Delay Line (VDL) The programmable delay unit is intended mainly for equalizing the signal delays at the individual channels of PMT before their delivery to the OR A and OR C circuits. Moreover, the VDL can be used for the choice of initial delay of TM and TVDC units, and it can be used in all other cases for precise remote tuning of delay.  Number of independent delay channels in the single unit: 4.  Standard of input and output signals: NIM.  Signal plug: SMC.  Step of delay tuning: 10 ps.  Range of delay tuning: 10 ns.  Control code: 10 bits. Parameters:

34 A. Klimov RRC KI Moscow 34 Charge-to-Time Converter (QTC)

35 A. Klimov RRC KI Moscow 35 Requirements for fast electronics  time resolution about 50 ps;  position (z-coordinate) resolution about 1.5 cm;  small dead time – less than 25 ns;  high counting rate of the order of ~2*10 5 s -1 ;  operation in magnetic field up to 0.5 Tesla;  good (up to 500 Krad) radiation hardness;  reasonable resolution of the multiplicity of charged particles.

36 A. Klimov RRC KI Moscow 36 UEP 5021 Specifications RFI-rejection (emission) CE:EN VDE 0871B, Mains inp. C or E otherwise EN EMC (immunity) CE:EN or 2 Operation temperature: °C without derating Storage:-30°C up to 85°C Temp.-coefficient:< 0.2% / 10K Stability (const. conditions):10mV or 0.1% within 24 hours 50mV or 1.0% within 6 month Current limits:15% of rated current-values, adjustable to any lower level (via fan tray switches or netware). Mains fuse can open in case of continuously overpowering! Voltage rise characteristics:monotonic 50ms, processor controlled. Complementary outputs with dual tracking Overvoltage crow bar protection: trip off adjusted to 125% of nominal voltage each output DC Off (trip off):within 5ms if >2% deviation from adjusted nominal values, after overload, overheat, overvoltage, undervoltage (bad status) and fan fail, output capacitors will be discharged by the crow bars temperature limits 110°C heat sink, 70°C ambient, trip off points adjustable, processor controlled. Efficiency:75% 2V/ -83% 5V/ -85% 12V and 15V-modules M T B F, 40°C ambient temperature: > h (UEL 4020 EC fan tray >45 000h)

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