1. Pirouz Bazargan SabetDecember 2003 RISC vs. CISC concept An implementation of Mips Implementation Concept of pipeline Pipeline’s problems

2. Pirouz Bazargan SabetDecember 2003 Problem with branches Beq The instruction that follows a branch is always fetched from the memroy Implementation

3. Pirouz Bazargan SabetDecember 2003 Implementation M @ IFC IR M IFC M IR DEC @ IR (BEQ) M delayed slot instruction

4. Pirouz Bazargan SabetDecember 2003 Implementation Solutions : Avoid the execution of the delayed slot instruction Hardware control Let the instruction be executed Difficulties in assembly language in contradiction with the RISC concept

5. Pirouz Bazargan SabetDecember 2003 Implementation The delayed slot instruction is always executed The compiler has to be tuned to the processor and put an instruction after each branch smart compiler branch useful instruction basic compiler branch nop

6. Pirouz Bazargan SabetDecember 2003 Implementation The later the next instruction address is calculated greater number of delayed slots hard to fill branch 75% used 5% used 0% used

7. Pirouz Bazargan SabetDecember 2003 Implementation The problem of data dependency

8. Pirouz Bazargan SabetDecember 2003 time 12345678910 i i+1 IDEMW IDEMW Add r3, r2, r1 Add r4, r3, r5 Implementation

9. Pirouz Bazargan SabetDecember 2003 Implementation Solutions : Try to resolve the problem inside the hardware Hardware control Let the compiler avoid the problem Difficulties inside the compiler

10. Pirouz Bazargan SabetDecember 2003 Add r3, r2, r1 Add r4, r3, r5 Implementation Add r4, r3, r5 time 12345678910 add r3 IDEMW IDEMW IDEMW IDEMW IDEMW add r4

11. Pirouz Bazargan SabetDecember 2003 Implementation Let the compiler avoid the problem Add r3, r2, r1 Add r4, r3, r5 nop Low performance nop

12. Pirouz Bazargan SabetDecember 2003 Implementation Try to resolve the problem inside the hardware i+1 ID time 12345678910 i IDEMW Add r3, r2, r1 Add r4, r3, r5 D EMW DD

13. Pirouz Bazargan SabetDecember 2003 E Implementation Are 3 wait cycles really necessary ? Add r3, r2, r1 Add r4, r3, r5 Data usage time 12345678910 i IDEMW MW i+1 ID E E

14. Pirouz Bazargan SabetDecember 2003 Implementation Are 3 wait cycles really necessary ? time 12345678910 i IDEMW Add r3, r2, r1 Add r4, r3, r5 Data availability

15. Pirouz Bazargan SabetDecember 2003 Implementation Putting all together time 12345678910 IDEMW Add r3, r2, r1 Add r4, r3, r5 IDEMW

16. Pirouz Bazargan SabetDecember 2003 Implementation Putting all together M +4 IFC DEC EXE MEM WBK IR S T + M Add r4, r3, r5 Add r3, r2, r1 IR + +4

17. Pirouz Bazargan SabetDecember 2003 Implementation All the data dependencies cannot be resolved time 12345678910 IDEMW Lw r3, 0(r1) Add r4, r3, r5 E MW i+1 ID E i

18. Pirouz Bazargan SabetDecember 2003 Implementation How many data dependencies time 12345678910 IDEMW i i+1 i+2 i+3 i+4 IDEMW IDEMW IDEMW IDEMW

19. Pirouz Bazargan SabetDecember 2003 Is there any limitation to deep pipelines ? NO !2 limitations deep pipeline great number of delayed slots complex hardware control due to data dependencies Implementation