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Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 7 – Registers and Register Transfer Logic and Computer Design Fundamentals

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Propagation Delay: capacitances introduce delay 2 All physical devices have delays due to the charging and discharging of (parasitic capacitors) and interconnection resistance. flow Resistive tube Crossing lines level t Propagation delay t pd

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Where to these capacitors come from? Most are parasitic caps 3 Crossing lines Cross section of Altera Stratix EP1S25 (TSMC process) 2um passivation M9 M8 M7 M6 M5 M4 M3 M2 M1 (Source: TSMC) Crossing interconnections (Source: IBM) 9 level of interconnections

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Review: 6-3 Flip-Flop Timing Parameters and metastability Edge triggered flip-flop If one violates the set-up time and hold time, the flip-flop can go in a metastable state. 4 C tStS thth In (D) set-up time C D Q Q In Out C hold time

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Metastable behavior Example of metastable behavior: After a while the flip-flop will go into a stable state (randomly). If this happens before the next clock edge, the actual circuits will see a defined input. The longer the clock period is the less chance of synchronization failure. Or use two synchronization flip-flops in series 5 metastable Eventually, the flip- flop will settle (Oscilloscope trace)

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PRACTICAL CONSIDERATIONS Debouncing 6

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Practical considerations In many cases the input signals come from push buttons and sensors: Switches exhibit bouncing Are not synchronous Give multiple input (sampled many times) This can give catastrophic failures of timing problems Solutions: Debounce the switch Synchronizer One-pulse circuit (and synchronizer) 7

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Bouncing of switches What is bouncing? When closing a switch, the switch contact bounces back and forth, giving multiple pulses 8 Causes spurious glitches on input B Measured signal A B chip Push button switch 5V

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Debouncing circuit The two resistors will keep S=R=0: Inputs are never floating Output does not bounce Q Q R S Push switch R S Q 5V contact to 5V Bouncing No bouncing SR latch Is set S=R=0 No change

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ISSUES WITH ASYNCHRONOUS INPUTS Likely violation of set up times 10

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Asynchronous inputs Asynchronous inputs (e.g. from sensors) can cause timing problems if set up time is violated: Use a synchronizer 11 Signal from sensor CLK t S setup time This setup time violation can give problems, such as metastability and erroneous operation: stable metastable

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Metastability and Synchronization A flip-flop can get into a metastable state: When the set-up or hold times are violated This can happen for asynchronous inputs (e.g. push button; sensor input, etc) 12 Input CLK Q0 Q1 Both flip flops behave differently! D Q D0i Q0 Sensor asynchronous input D Q D1 Q1 CLK kick Q0Q0 Q0Q0 Q1Q1

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Metastability (continued) Asynchronous inputs: Use a synchronizing flip-flop Now, only the synchronizer may get into the metastable state; however, there is a good chance that by the end of the clock period it went into one of the stable states. 13 D Q D0 Q0 D Q D1i Q1 D Q Di Ai Synchronizer Asynchronous input

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Synchronizer 14 D Q Di Ai CLK Sensor,async Synchronized output Signal from sensor CLK Synchronized output Note: by having the sensor input enter through a single D flip-flop the problem of timing circuits is reduced greatly (there is still a small chance that the D FF will be unstable). By using two D flip-flops in series one further reduces the risk that the 2 nd FF will be metastable.

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Chapter 7 Registers and Register Transfers 15 (Source: reference.findtarget.com)

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7-1 Registers Register – a collection of flip-flops, together with some combinational logic, that performs data processing tasks (e.g. storing, moving data, etc). In theory, a register is sequential logic which can be defined by a state table. More often think of a register as storing a vector of binary values. 16

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Simple Storage Register A D flip-flop register loads information on every clock cycle! To “store” or “load” information should be controlled by a signal. 17 Outputs Active low Clear (asynch) inputs

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Register with Parallel Load: Clock Gating Use a signal to block the clock to the register Load is a frequent name for the signal that controls register storage and loading Load = 1: Load the values on the data inputs Load = 0: Store the values in the register 18 Extra edge! Clock Load Gated Clock to FF Timing: 1 Gated clock: To C input of Flip-flops Clock gating:

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Registers with Load-Controlled Feedback A more reliable way to selectively load a register: Run the clock continuously, and Selectively use a load control to change the register contents. Example: 2-bit register with Load Control: For Load = 0, loads register contents (hold current values) For Load = 1, loads input values (load new values) Hardware more complex than clock gating, but free of timing problems 19 C D Q C D Q Clock In0 In1 A1 A0 Y1 Y0 Load 2-to-1 Multiplexers

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Registers with Load Control: Example 20 K1=1: R1 stores the result of addition/subtraction

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7-2 Register Transfers The data is stored in registers, which compose the datapath. In many cases one wants to perform a variety of arithmetic and logical operations on a set of data bits (e.g. a 16-bit word): Additions, subtraction, shifting, loading, etc. 21 (Source: reference.findtarget.com)

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Register Transfers Operations The type of operations on the data will be determined by a controller, often called a control unit. This division between the datapath and control unit makes the design of complex systems easier. Strategy: divide and conquer! Registers play a key role in complex digital systems! Transfers between registers determine the operations. 22 (Source: reference.findtarget.com)

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Datapath and Control Unit 23 Stores data in registers Performs operations on data, specified by Cntr unit Provide status signals Is defined by registers and its operations: Register Transfer Operations (RTL) An elementary operation: microoperation Determines which operation and sequence of operation based on status signals Control signals: activate various operations in the datapath Is a large finite state machine Control Unit Datapath Control signals Status signals

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7-3 Register Transfer Operations Register Transfer Operations – The movement and processing of data stored in registers Three basic components: set of registers operations control of operations Elementary Operations -- load, count, shift, add, bitwise "OR", etc. Elementary operations called microoperations PC(H) PC(L) R2 Ex. 8-bit register R: 16-bit registers: R 7 …1 0 LSB MSB Register Notation:

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Conditional Transfer If (K1 =1) then (R2 R1) is shortened to K1: (R2 R1) where K1 is a control variable specifying a conditional execution of the microoperation. 25 R1R2 K 1 Clock Load n Clock K1K1 Transfer occurs here No Transfers Occur Here Transfer occurs here No Transfers Occur Here Clock K1K1

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7-5 Microoperations Logical Groupings: Transfer - move data from one set of registers to another Arithmetic - perform arithmetic on data in registers Logic - manipulate data or use bitwise logical operations Shift - shift data in registers Arithmetic operations + Addition – Subtraction * Multiplication / Division 26 Logical operations (bitwise) Logical OR Logical AND Logical Exclusive OR Not

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Example Microoperations Add the content of R1 to the content of R2 and place the result in R1. R1 R1 + R2 Multiply the content of R1 by the content of R6 and place the result in PC. PC R1 * R6 Exclusive OR the content of R1 with the content of R2 and place the result in R1. R1 R1 R2 27

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Example Microoperations (Continued) On condition K1 OR K2, the content of R1 is Logic bitwise ORed with the content of R3 and the result placed in R1: (K1 + K2): R1 R1 R3 NOTE: "+" (as in K 1 + K 2 ) and means “OR.” In R1 R1 + R3, + means “plus.” 28

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Arithmetic Microoperations Note that any register may be specified for source 1, source 2, or destination. These simple microoperations operate on the whole word 29

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Implementation of an Arithmetic Micro operation 30 X K1 : R1 R1 + R2 X K1 : R1 R1 + R2 + 1 Conditional microoperation: Condition

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Logical Microoperations 31 Symbolic Designation Description R0 R1 Bitwise NOT R0 R1 R2 Bitwise OR (sets bits) R0 R1 R2 Bitwise AND (clears bits) R0 R1 R2 Bitwise EXOR (complements bits)

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Logical Microoperations (continued) Let R1 = , and R2 = Then after the operation, R0 becomes: 32 (sets bits) (clears bits) (complements bits)

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Shift Microoperations Let R2 = Then after the operation, R1 becomes: 33 Symbolic Designation Description R1 sl R2 Shift Left R1 sr R2 Shift Right R1 Operation R1 sl R R1 sr R2 Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data shifted in, or to “catch” the data shifted out. Other shifts are possible (rotates, arithmetic).

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7-6: Microoperation on a Single Register Microoperation on a Single Register MUX-based transfers Shift registers (needed for Lab) Ripple Counter Synchronous binary counter Other counters 34

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7-6 Microoperations on a Single Register The focus is on the implementation of microperations with a SINGLE register as the Destination of the results In addition to the register there is some combinational logic needed. This is considered part of the register and is called DEDICATED logic (in contrast to SHARED logic for multiple destination registers). Multiplexer-based transfer: makes use of multiplexers to allow multiple operations on a single destination register (See next) 35

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Multiplexer-Based Transfers Multiplexers connected to register inputs produce flexible transfer structures Consider the following circuit What are the corresponding Register Transfer operations of the following implementation? 36 Load R0 n MUX S K Load n n K 1 R2 R1 Combinational circuit

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Register Transfer Operations implemented by the following circuit K1.K2: R0 R1 K1.K2: R0 R2 37 Load R0 n MUX S K Load n n K 1 R2 R1

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Exercise Consider the following circuit (Note: Clocks are omitted for clarity) What are the corresponding Register Transfer operations? 38 Load R0 n MUX S K Load n n K 1 R2 R1

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Shift Registers Shift Registers move data laterally within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this: Data input, In, is called a serial input or the shift right input. Data output, Out, is often called the serial output. The vector (A, B, C, Out) is called the parallel output. 39

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Shift Registers (continued) The behavior of the serial shift register is given in the listing on the lower right T0 is the register state just before the first clock pulse occurs T1 is after the first pulse and before the second. Initially unknown states are denoted by “?” Complete the last three rows of the table 40 DQDQDQDQ In Clock CP A B C Out

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Shift Registers (continued) 41 DQDQDQDQ In Clock CP A B C Out

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Parallel Load Shift Registers By adding a mux between each shift register stage, data can be shifted or loaded If SHIFT is low, A and B are replaced by the data on D A and D B lines, else data shifts right on each clock. By adding more bits, we can make n-bit parallel load shift registers. Register Transfer Operation: 42 D Q D Q AB CP SHIFT IN DADA DBDB MUX SHIFT: Q sr Q SHIFT’: Q D

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Parallel Load Shift Registers with Load 43 Use a multiplexer with 3 inputs: S1 S0 Shift Load Serial input D0D0 = D Q S1 S0 Shift Load C D Q S1 S0 Shift Load C Q0Q0 Q1Q1 Q2Q2 D0D0 D1D1 D2D2 Serial input D Q S1 S0 Shift Load C Control

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Timing 44 (Shift = 0) Register Transfer Operation: Shift: Q sl Q Shift.Load: Q D Clock Load Di Qi Output changes here

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Bidirectional shift register 45

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Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: Ripple Counters Clock is connected to the flip-flop clock input on the LSB bit flip-flop For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous Output change is delayed more for each bit toward the MSB. Resurgent because of low power consumption Synchronous Counters Clock is directly connected to the flip-flop clock inputs Logic is used to implement the desired state sequencing 46

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Ripple Counter How does it work? When there is a positive edge on the clock input of A, A complements The clock input for flip- flop B is the complemented output of flip-flop A When flip A changes from 1 to 0, there is a positive edge on the clock input of B causing B to complement 47 Reset Clock D D CRCR CRCR B A B CP A

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Ripple Counter (continued) The arrows show the cause-effect relation- ship from the prior slide => The corresponding sequence of states => (B,A) = (0,0), Each additional bit, C, D, …behaves like bit B, changing half as frequently as the bit before it. For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), … 48 (1,0), (0,1), (0,1), … (0,0), (1,1), CP B A

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Delays in a Ripple Counter Starting with C = B = A = 1, the next clock increments the count to (C,B,A) = 0; thus from (111) to (000) In fine timing detail: The clock to output delay t PHL causes an increasing delay from clock edge for each stage transition. Thus, the count “ripples” from least to most significant bit. For n bits, total worst case delay is n t PHL. 49 CP A B C t PHL t pHL

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Ripple Counter (continued) These circuits are called ripple counters because the changes “ripple” through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. Disadvantages: Slow operation due to the delays Intermediate results with can give rise to unreliable operation in digital circuits Advantages: Simple hardware Low power consumption 50

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Synchronous Counters To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => 51 D3Q3 D2 Q2 D1 Q1 D0Q0 Clock Incre- menter A3 A2 A1 A0 S3 S2 S1 S0 Comb. Logic

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Synchronous counter 52 Q Q2 1 1 Q 0 : changes at every clock When EN=1: XOR inverts and Q 0 =D’ D Q C EN Q0Q0 Q 1 : changes when Q 0 = 1: D Q C EN Q1Q1 Q0Q0 Q 2 : changes when Q 0 and Q 1 = 1 D Q C Q2Q2 Q1Q1 Clock Q0

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Synchronous counter – parallel gating 53 Carry Out CO Incrementer Replace AND carry chain with ANDs => in parallel Advantages Reduces path delays Called parallel gating Like carry lookahead Symbol:

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Synchronous Counter with an Arbitrary Sequence Start with the state diagram or the state table Decide which flip- flops to use Find the combinational logic (inputs to the flip- flops) Draw or build the circuit

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Design Exercise: Arbitrary Sequence

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Arbitrary Count sequence: next state equation 3 Flip-flops required Find the next state equations: D C, D B, D A. 56 A B C DCDC 1 0 x 0 A B C DBDB 0 1 x 0 A B C DADA 0 0 x x 0 D A = A’B+AB’ = A B D B = C D C = B’C’ Be careful with Table sequence

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Counter schematic 57 D A = A’B+AB’ = A B D B = C D C = B’C’ What about unused states? Complete the state diagram

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