Presentation on theme: "IKI10230 Pengantar Organisasi Komputer Bab 10: Micro Architecture"— Presentation transcript:
1IKI10230 Pengantar Organisasi Komputer Bab 10: Micro Architecture Sumber: 1. Paul Carter, PC Assembly Language 2. Hamacher. Computer Organization, ed-5 3. Materi kuliah CS61C/2000 & CS152/1997, UCB5 Mei 2004L. Yohanes Stefanus Bobby Naziefbahan kuliah:
2Prosesor: Control & Datapath Processor(active)ComputerControl(“brain”)Datapath(“brawn”)Memory(passive)(whereprograms,datalive whenrunning)DevicesInputOutputThat is, any computer, no matter how primitive or advance, can be divided into five parts:1. The input devices bring the data from the outside world into the computer.2. These data are kept in the computer’s memory until ...3. The datapath request and process them.4. The operation of the datapath is controlled by the computer’s controller.All the work done by the computer will NOT do us any good unless we can get the data back to the outside world.5. Getting the data back to the outside world is the job of the output devices.The most COMMON way to connect these 5 components together is to use a network of busses.
153. Lakukan operasi penjumlahan MDRout, Add, ZinY=[R1]ZMDR=[[R3]]MARPCTEMPR3R1IRInstructionDecoderALUAddress linesData linesAddCarry-inZin
164. Simpan hasil penjumlahan Zout, R1in, EndY=R1Z=[R1]+[[R3]]MDR=M[R3]MARPCTEMPR3R1IRInstructionDecoderALUAddress linesData lines
17Tahapan Eksekusi “Branching” Unconditional (JMP Loop)PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, ZinZout, PCin, WMFCMDRout, IRinPCout, YinOffset-field-of-IRout, Add, Zin // PC [PC] + OffsetZout, PCin, EndConditional (contoh: JS Loop)PCout, Yin , If SF=0 then End // take the branch?
34Multiple-bus: salah satu cara peningkatan kinerja MDRMARPCTEMPRegisterFileIRInstructionDecoderALUABCData linesAddress linesMemory BusAdd R1,R2,R3 ;R1[R2]+[R3]
35Bandingkan dengan Organisasi Single-bus YZMDRMARPCTEMPR3R1IRInstructionDecoderALUR2Add R1,R2,R3 ;R1[R2]+[R3]
36Beberapa Teknik Peningkatan Kinerja Prosesor Lainnya Pre-fetching: instruksi berikutnya (i+1) di-fetch pada waktu pengeksekusian instruksi (i)Perlu teknik “Branch Prediction”Pipelining: eksekusi instruksi dipecah kedalam tahap-tahap yang dapat dilakukan secara “overlap”Fetch InstruksiDecode InstruksiBaca Operand (dari register asal)Lakukan OperasiTulis Hasil (ke register tujuan)On-chip Cache: mempercepat akses data dari/ke memori
39Input & Output Gating Operasi Tulis Operasi Baca 1-bit bus Zin Q 1 bit line of common busZinZout3-state switchSR_QQoutput: 1, 0, open-circuitoperasi tulis & baca dilakukan secara bergantianmemungkinkan peranti lain menggunakan busOperasi TulisOperasi Baca1-bit bus Zin QX 0 QZout Q output0 X 3-state
41Komponen-komponen Waktu Eksekusi Waktu Eksekusi Ditentukan Oleh:Gate DelayWaktu yang dibutuhkan output suatu gerbang logika berubah sesuai kondisi inputnyaRegister’s DelayWaktu yang dibutuhkan isi register berubah sesuai inputnya
42Waktu Eksekusi: Gate Delay When input 0 1, output 1 0 but NOT instantlyOutput goes 1 0: output voltage goes from Vdd (5v) to 0vWhen input 1 0, output 0 1 but NOT instantlyOutput goes 0 1: output voltage goes from 0v to Vdd (5v)Voltage does not like to change instantaneouslyVoltageVout1 => VddVinYou may ask yourself, why am I sitting here listening to all these transistors stuff while I am registered for a computer science class?Well the reason is that we want to teach you to be a computer engineer, not a scientist.As an engineer, you need to know the limitations God placed on the non-ideal world.More specifically, let’s look at an inverter.When the Inverter’s input goes from 0 to 1, the output of the inverter will go from 1 to 0, but not instantly. The voltage will drop from 5v to 0 gradually as shown in this plot.Similarly, when the inverter’s input goes from 1 to 0, the output of the inverter will go from 0 to 1, but once again, NOT instantly. It will go from 0v to 5V gradually as shown here.The bottom line here is that voltage, like any other physical quantities, does not like to change instantaneously.+2 = 27 min. (Y:07)OutIn0 => GNDTime
43Waktu Eksekusi: Series Connection VddVddCoutVoutV1VinVoutVinV1G1G2G1G2C1VoltageVddV1VoutVinVdd/2d1d2GNDSo far, we have look at the delay of one gate. But any system with only one gate is really not a very interesting system.So let’s look at a more interesting system with two gates. For simplicity, I am representing the two gates as two inverters.The total delay of this system will be the sum of the delay of these two gates.More specifically, if we apply a step low to high transition at the input of the first gate, its output will go from high to low gradually and after a delay of d1, it will have fallen to Vdd/2.At some point during this transition (points to V1 going H -> L), the PMOS transistor of the second inverter will start conducting and start driving the output toward 5v.For simplicity, we have decided to measure the delay from the point when V1 and Vout reaches Vdd/2.The last thing I want to point out on this slide is the capacitor between the two inverters.You know, those EE guys are pretty smart sometimes. They draw two parallel lines at the transistor’s gate for a reason--to remind us there is some capacitance at the gate.Therefore the capacitance value of this capacitor come from TWO sources. Capacitance of the wire connecting the gates. And the gate capacitance of the NMOS and PMOS transistors inside the second inverter.+2 = 32 min. (Y:12)TimeTotal Propagation Delay = Sum of individual delays = d1 + d2Capacitance C1 has two components:Capacitance of the wire connecting the two gatesInput capacitance of the second inverter
44Waktu Eksekusi: Register’s Delay QDon’t CareClkUnknownSetupHoldClock-to-QClkSetup Time: Input must be stable BEFORE the trigger clock edgeHold Time: Input must REMAIN stable after the trigger clock edgeClock-to-Q time:Output cannot change instantaneously at the trigger clock edgeSo far we have been looking at combinational logic, let’s look at the timing characteristic of a storage element.The storage element you will use is a D type flip-flop trigger on the negative clock edge.In order for the data to latch into the flip flop correctly, the input must be stable slightly before the falling edge of the clock. This time is called the Setup time.After the clock edge has arrived, the data must remain stable for a short amount of time AFTER the trigger clock edge. This is called the hold time.The output cannot change instantaneously at the trigger clock edge. The time it takes for the output to change to its new value after the clock is called the Clock-to-Q time.Similar to delay in logic gates, the Clock-to-Q time has two components:(a) The internal Clock-to-Q time: the time it takes the output to change if output load is zero.(b) And the load dependent Clock-to-Q time.+2 = 50 min. (Y:30)
45Waktu Eksekusi R2out, Add, Zin Turn-on time for 3-state driver YZRiALUABXRiinRioutYinYoutZinZoutAddTurn-on time for 3-state driverTransmission timePropagation delay through ALUSetup timeHold time