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1 IKI10230 Pengantar Organisasi Komputer Bab 10: Micro Architecture Sumber: 1. Paul Carter, PC Assembly Language 2. Hamacher. Computer Organization, ed-5.

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Presentation on theme: "1 IKI10230 Pengantar Organisasi Komputer Bab 10: Micro Architecture Sumber: 1. Paul Carter, PC Assembly Language 2. Hamacher. Computer Organization, ed-5."— Presentation transcript:

1 1 IKI10230 Pengantar Organisasi Komputer Bab 10: Micro Architecture Sumber: 1. Paul Carter, PC Assembly Language 2. Hamacher. Computer Organization, ed-5 3. Materi kuliah CS61C/2000 & CS152/1997, UCB 5 Mei 2004 L. Yohanes Stefanus Bobby Nazief bahan kuliah:

2 2 Prosesor: Control & Datapath Processor (active) Computer Control (“brain”) Datapath (“brawn”) Memory (passive) (where programs, data live when running) Devices Input Output

3 3 Organisasi Prosesor (Single-bus) Y Z MDR MAR PC TEMP R(n-1) R0 IR Instruction Decoder ALU Carry-in Add Sub XOR Address lines Data lines Control lines Memory bus ALU control lines Control Unit Datapath Unit

4 4 Legenda °PC:Program Counter °MAR:Memory Address Register °MDR:Memory Data Register °ALU:Arithmetic & Logic Unit °IR:Instruction Register °SP:Stack Pointer

5 5 Eksekusi instruksi yang ukurannya tetap do { 1. IR  [[PC]]// Fetch instruksi 2. PC  [PC] + d// Tunjuk ke lokasi instruksi berikutnya 3. Eksekusi instruksi } while (!stop) Eksekusi instruksi yang ukurannya bervariasi do { do {// Fetch instruksi IR  [[PC]] PC  [PC] + d } while (!end-of-instruction) Eksekusi instruksi } while (!stop) Siklus Eksekusi Instruksi

6 6 Operasi-operasi Dasar Dalam Eksekusi Instruksi °Pertukaran Data Antar-Register °Operasi Aritmatika & Logika di Datapath °Mengambil (fetching) Data dari Memori °Menyimpan (storing) Data ke Memori

7 7 Pertukaran Data Antar-Register Instruksi: MOV R4,R1 ; R4  [R1] Langkah-langkah: 1.Enable output of R1 // setting R1 out to 1 2.Enable input of R4 // setting R4 in to 1 R4 R1 X X X X R1 in R1 out R4 in R4 out

8 8 Operasi Aritmatika dan Logika Instruksi: ADD R1,R2 ; R1  [R1] + [R2] Langkah-langkah: 1.R1 out, Y in 2.R2 out, Add, Z in 3.Z out, R1 in Y Z Ri ALU A B X X X X X X Ri in Ri out Y in Y out Z in Z out Add

9 9 Mengambil Data dari Memori Instruksi: MOV R2,[R1]; R2  [[R1]] Langkah-langkah: 1.MAR  [R1] 2.Read 3.Tunggu sinyal MFC // MFC = Memory Function Completed // Pada saat MFC aktif: // MDR  M[MAR] 4.R2  [MDR] Y Z MDR MAR PC TEMP R2 R1 IR Instruction Decoder ALU Carry-in Add Sub XOR Address lines Data lines Read MFC

10 10 Menyimpan Data ke Memori Instruksi: MOV [R1],R2; [R1]  [R2] Langkah-langkah: 1.MAR  [R1] 2.MDR  [R2], Write 3.Tunggu sinyal MFC // MFC = Memory Function Completed // Pada saat MFC aktif: // M[MAR]  MDR Y Z MDR MAR PC TEMP R2 R1 IR Instruction Decoder ALU Carry-in Add Sub XOR Address lines Data lines Write MFC

11 11 Langkah-langkah Pengeksekusian Instruksi

12 12 Tahapan Eksekusi Instruksi Instruksi: AddR1,[R3]; R1  [R1] + [[R3]] Langkah-langkah: 1.Fetch instruksi 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 2.Fetch operand (isi lokasi memori yg ditunjuk oleh R3) 4.R3 out, MAR in, Read 5.R1 out, Y in, WMFC 3.Lakukan operasi penjumlahan 6.MDR out, Add, Z in 4.Simpan hasil penjumlahan di R1 7.Z out, R1 in, End

13 13 1. Fetch instruksi 1. PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2. Z out, PC in, WMFC 3. MDR out, IR in Y Z MDR MAR PC TEMP R3 R1 IR Instruction Decoder ALU Carry-in Add Address lines Data lines Control lines [PC]+1

14 14 2. Fetch operand Y Z MDR MAR PC=[PC]+1 TEMP R3 R1 IR Instruction Decoder ALU Address lines Data lines 4. R3 out, MAR in, Read 5. R1 out, Y in, WMFC

15 15 3. Lakukan operasi penjumlahan Y=[R1] Z MDR=[[R3]] MAR PC TEMP R3 R1 IR Instruction Decoder ALU Address lines Data lines Carry-in Add Z in 6.MDR out, Add, Z in

16 16 4. Simpan hasil penjumlahan Address lines Data lines Y=R1 Z=[R1]+[[R3]] MDR=M[R3] MAR PC TEMP R3 R1 IR Instruction Decoder ALU 7.Z out, R1 in, End

17 17 Tahapan Eksekusi “Branching” Unconditional (JMP Loop) 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.PC out, Y in 5.Offset-field-of-IR out, Add, Z in // PC  [PC] + Offset 6.Z out, PC in, End Conditional (contoh: JS Loop) 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.PC out, Y in, If SF=0 then End// take the branch? 5.Offset-field-of-IR out, Add, Z in // PC  [PC] + Offset 6.Z out, PC in, End

18 18 MOV EAX,[EBX]

19 19 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EBX out, MAR in, Read 5.WMFC 6.MDR out, EAX in, End Y Z MDR MAR PC TEMP EAX EBX IR Instruction Decoder ALU Set Carry-in Add Address lines Data lines Control lines [PC]+1 Tahapan Eksekusi Instruksi: MOV EAX,[EBX] PC out Read MAR in Z in Clear Y

20 20 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EBX out, MAR in, Read 5.WMFC 6.MDR out, EAX in, End Tahapan Eksekusi Instruksi: MOV EAX,[EBX] Y Z = [PC]+1 MDR MAR PC TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines Z out WMFC PC in

21 21 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EBX out, MAR in, Read 5.WMFC 6.MDR out, EAX in, End Tahapan Eksekusi Instruksi: MOV EAX,[EBX] Y Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines MDR out IR in

22 22 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EBX out, MAR in, Read 5.WMFC 6.MDR out, EAX in, End Tahapan Eksekusi Instruksi: MOV EAX,[EBX] Y Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines Read MAR in EBX out

23 23 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EBX out, MAR in, Read 5.WMFC 6.MDR out, EAX in, End Tahapan Eksekusi Instruksi: MOV EAX,[EBX] Y Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines WMFC

24 24 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EBX out, MAR in, Read 5.WMFC 6.MDR out, EAX in, End Tahapan Eksekusi Instruksi: MOV EAX,[EBX] Y Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines MDR out EAX in

25 25 ADDEAX,EBX

26 26 Tahapan Eksekusi Instruksi: ADD EAX,EBX Instruksi: ADDEAX,EBX; EAX  [EAX] + [EBX] Langkah-langkah: 1.Fetch instruksi 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 2.Fetch operand ke-1 (EAX) 4.EAX out, Y in 3.Fetch operand ke-2 (EBX) dan Lakukan operasi ALU 5.EBX out, Add, Z in 4.Simpan hasil penjumlahan di EAX 6.Z out, EAX in, End

27 27 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EAX out, Y in 5.EBX out, Add, Z in 6.Z out, EAX in, End Y Z MDR MAR PC TEMP EAX EBX IR Instruction Decoder ALU Set Carry-in Add Address lines Data lines Control lines [PC]+1 Tahapan Eksekusi Instruksi: ADD EAX,EBX PC out Read MAR in Z in Clear Y

28 28 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EAX out, Y in 5.EBX out, Add, Z in 6.Z out, EAX in, End Tahapan Eksekusi Instruksi: ADD EAX,EBX Y Z = [PC]+1 MDR MAR PC TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines Z out WMFC PC in

29 29 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EAX out, Y in 5.EBX out, Add, Z in 6.Z out, EAX in, End Tahapan Eksekusi Instruksi: ADD EAX,EBX Y Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines MDR out IR in

30 30 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EAX out, Y in 5.EBX out, Add, Z in 6.Z out, EAX in, End Tahapan Eksekusi Instruksi: ADD EAX,EBX Y Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines Y in EAX out

31 31 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EAX out, Y in 5.EBX out, Add, Z in 6.Z out, EAX in, End Tahapan Eksekusi Instruksi: ADD EAX,EBX Y=EAX Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines Z in EBX out Add

32 32 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.EAX out, Y in 5.EBX out, Add, Z in 6.Z out, EAX in, End Tahapan Eksekusi Instruksi: ADD EAX,EBX Y=EAX Z MDR MAR [PC]+1 TEMP EAX EBX IR Instruction Decoder ALU Address lines Data lines Control lines EAX in Z out

33 33 Peningkatan Kinerja Prosesor

34 34 Multiple-bus: salah satu cara peningkatan kinerja MDR MAR PC TEMP Register File IR Instruction Decoder ALU A B C Data lines Address lines Memory Bus Add R1,R2,R3 ;R1  [R2]+[R3]

35 35 Bandingkan dengan Organisasi Single-bus Add R1,R2,R3 ;R1  [R2]+[R3] Y Z MDR MAR PC TEMP R3 R1 IR Instruction Decoder ALU R2

36 36 Beberapa Teknik Peningkatan Kinerja Prosesor Lainnya °Pre-fetching: instruksi berikutnya (i+1) di-fetch pada waktu pengeksekusian instruksi (i) Perlu teknik “Branch Prediction” °Pipelining: eksekusi instruksi dipecah kedalam tahap-tahap yang dapat dilakukan secara “overlap” Fetch Instruksi Decode Instruksi Baca Operand (dari register asal) Lakukan Operasi Tulis Hasil (ke register tujuan) °On-chip Cache: mempercepat akses data dari/ke memori

37 37 LAMPIRAN

38 38 Gating: Controlling Data Access from/to a Gate

39 39 Input & Output Gating 1 bit line of common bus Z in Z out 3-state switch S R _Q_Q Q output: 1, 0, open-circuit 1-bit busZ in Q X 0Q Z out Qoutput 0 X3-state Operasi Tulis Operasi Baca memungkinkan peranti lain menggunakan bus operasi tulis & baca dilakukan secara bergantian

40 40 Komponen-komponen Waktu Eksekusi

41 41 Komponen-komponen Waktu Eksekusi °Waktu Eksekusi Ditentukan Oleh: Gate Delay -Waktu yang dibutuhkan output suatu gerbang logika berubah sesuai kondisi inputnya Register’s Delay -Waktu yang dibutuhkan isi register berubah sesuai inputnya

42 42 Waktu Eksekusi: Gate Delay °When input 0  1, output 1  0 but NOT instantly Output goes 1  0: output voltage goes from Vdd (5v) to 0v °When input 1  0, output 0  1 but NOT instantly Output goes 0  1: output voltage goes from 0v to Vdd (5v) °Voltage does not like to change instantaneously OutIn Time Voltage 1 => Vdd 0 => GND Vout Vin

43 43 Waktu Eksekusi: Series Connection °Total Propagation Delay = Sum of individual delays = d1 + d2 °Capacitance C1 has two components: Capacitance of the wire connecting the two gates Input capacitance of the second inverter Vdd Cout Vout Vdd C1 V1Vin V1VinVout Time G1G2G1G2 Voltage Vdd Vin GND V1 Vout Vdd/2 d1d2

44 44 Waktu Eksekusi: Register’s Delay °Setup Time: Input must be stable BEFORE the trigger clock edge °Hold Time: Input must REMAIN stable after the trigger clock edge °Clock-to-Q time: Output cannot change instantaneously at the trigger clock edge DQ DDon’t Care Clk UnknownQ SetupHold Clock-to-Q Clk

45 45 Waktu Eksekusi Y Z Ri ALU A B X X X X X X Ri in Ri out Y in Y out Z in Z out Add Turn-on time for 3-state driver Transmission time Propagation delay through ALU Setup time Hold time R2 out, Add, Z in


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