1. Liquid Processor Platform
The goal of this project is to develop a soft core embedded processor system that can be programmed via a network connection.
This platform is to be used as the based system for a larger “Liquid Architecture” project that will make modifications to the Leon processor for experimental purposes.
Visit:

2. Team Members Phillip Jones (team leader)
High-level hardware architecture
Shobana Padmanabhan
Control Software development
John Maschmeyer
SDRAM controller interface
Daniel Rymarz
Cross-compiler, Executable -> IP packet formatting

3. Layered Protocol Wrappers
SOC Block Diagram
Off-Chip
SRAM/SDRAM 1
SRAM/SDRAM 1
Controller
Leon Controller
Control Packet
Processor
(cpp)
(Modified MP3)
Alert Generator
(Modified MP3)
LEON
system
Layered Protocol Wrappers

4. LEON system ICACHE DCACHE To Leon Controller Boot Rom Key LEON
Processor
ICACHE DCACHE
Data / Address
Memory
Controller
To Leon
Controller
UART
AHB
Serial port
APB
Adapter
Boot
Rom
LED Driver
LEDs
Key
Present
Modified

5. Motivation Soft-core embedded Processor:
Very flexible processor that would be useful for quickly prototyping systems with different parameters (e.g. pipe-line depth, cache size, hardware-accelerated instructions, etc.) to perform performance evaluations
Programmable / Configurable over a Network:
Motivated by the desire to integrate the soft-core processor into the FPX environment (FPX environment will provide an infrastructure for dynamic reconfiguration)

6. References & Related Work
The base Leon system used in this project can be downloaded from
Other projects that have used the Leon system

7. Design Approach Start with Leon Processor base
Supplies many of the components that will be needed in the end system.
Soft-core processor
Memory controller
General I/O Drivers (for Liquid “Architecture Project”)
System/Processor Bus (AMBA)
Develop and Integrate new features
Control SW
Modify Boot ROM
AMBA to SDRAM Controller Adapter
Control Packet routing (MP3 cpp as base)
Validation Environment (MP3 Testbench as base)

8. Layered Protocol Wrappers
SOC Block Diagram
Off-Chip
SRAM/SDRAM 1
SRAM/SDRAM 1
Controller
Leon Controller
Control Packet
Processor
(cpp)
(Modified MP3)
Alert Generator
(Modified MP3)
LEON
system
Layered Protocol Wrappers

9. Design Data New/Modified Entities External Memory Interfaces
LEON Controller
Control LEON access to memory / Start of program execution
LEON Boot ROM
modified to poll a given memory address at boot up
LEON Memory Controller
modified to interface with FPX SDRAM
External Memory Interfaces
1 SRAM/SDRAM Interface
Estimated Size
Number of LUTs: ,277 (31%)
Number of Slices: (41%)
Number of BlockRAMs: (33%)
Synthesis Frequence: 30 MHz

10. Tasks Config/Build/Validation Environment Control Packet Process
Configuration of Leon system
Cache size, MMU, Memory access wait states …
Integration of Leon system into MP3 validation environment
Control Packet Process
Direct the appropriate Control packets to Leon Controller (Read/Write SRAM, Start program, …)
SDRAM Interface
Needed if larger applications such as Linux are to be run on the Liquid processor system

11. Tasks (cont.) Control SW
Automate tasks (e.g. Load Program, read/write RAM location “x”, Reset Processor, …)
Definition of control packets
Sparc Assembly programming & Cross-compiler code generation
Develop test programs for Leon to execute
conversion of executable into IP packet payload

12. Implementation & Testing
Hardware
Leon Controller
Leon Processor
SDRAM interface
Software
Control software
Cross-compiler, executable conversion

13. Leon Boot Check Message to user “LEON READY” SRAM data_in data_out
Monitor
‘Z’
SRAM_OE
CpuData
Leon Processor
CpuAddr

14. Leon Control Hardware Message to user “LEON READY” SRAM data_in
data_out
Leon Control
State Machine
Check for
CpuAddr = CheckReady
‘0’
LeonGo
CpuAddr
LeonGo
UserAddr
‘Z’
LeonGo
UserStart
SRAM_OE
CpuData
UserData
Leon Processor
CpuAddr

15. Simple “User” Emulation
Send result to user
(via IP packet)
SRAM
Leon Control
State Machine
&
User Emulation
data_in
data_out
‘0’
LeonGo
CpuAddr
LeonGo
‘Z’
LeonGo
UserAddr
SRAM_OE
CpuData
UserData
Leon Processor
CpuAddr

16. Boot Rom Modifications
Set Config registers
Set Config registers
Set up dedicated SRAM space
Set up dedicated SRAM space
Wait for
UART Event
Wait for
Go Leon
flush
Load: ld reg value
CheckReady: ld reg ProgAddr
btst 1 reg
cmp 0 reg
be “Load”
be “CheckReady”
nop
jmp reg
Original Leon Boot code
Modified Leon Boot code

17. Motivation for SDRAM SRAM - 1 MB, SDRAM - 64 MB
Large Programs will need the extra memory space
SRAM solution uses existing LEON memory outputs
Easy to implement
Performance is limited
For Better Performance, connect directly to AMBA bus
Requires modifying LEON
More difficult to implement
Allows for performance enhancements

18. SDRAM Adapter: Overview
FPX SDRAM Controller
Arbitrated support for up to 3 modules
Support for Sequential Bursts of fixed length
64-bit bus to SDRAM
AMBA AHB Bus
Support for sequential and non-sequential bursts of unspecified length
32-bit wide data bus

19. SDRAM Adapter: Design Must handle protocols for both sides
Operate as an AMBA AHB slave
Handle Handshaking with SDRAM Controller
Difference in bus width causes some problems
Reads can simply return correct 32-bit segment
Writes must first read full 64-bits, then modify only correct segment

20. SDRAM Adapter: Support for bursts
Controller cannot handle non-sequential bursts
Handshake required between each access
Sequential bursts are limited by unspecified burst length
Simulations seem to indicate that bursts tend to be no longer than 4 32-bit words
Solution: Design for bursts of 4 32-bit words
No real loss for shorter bursts
Longer bursts will require an additional handshake
Write bursts cannot occur

21. Control S/W Architecture
H/W
Internet
Java Emulator
of the H/W
(for debugging)
1. Compile w/ GCC
2. Assemble w/ GAS
3. Link w/ LD
4. Convert to bin w/ OBJCOPY
5. Convert to IP w/ Forth program
1. Upload the IP from the prev step
2. Enter other UDP parameters
Java Servlet (running on Apache TomCat)
acting asUDP Client

22. Control S/W web page

23. Java Server receiving the UDP packet

24. Control packet for write
Control packet for memory write = x64
Control packet for write
32 bits
Ver
IHL
Type of service
Total length
Identification
Flags
Fragment offset
TTL
Protocol
Header checksum
Source address
Destination address
Source port
Destination port
Length
Checksum
Opcode
String length
Packet sequence number
Memory address
Byte 4
Byte 3
Byte 2
Byte 1
Byte N - 3
Byte N - 2
Byte N - 1
Byte N

25. Control packet for start = x50, halt = x54 CPU
32 bits
Ver
IHL
Type of service
Total length
Identification
Flags
Fragment offset
TTL
Protocol
Header checksum
Source address
Destination address
Source port
Destination port
Length
Checksum
Opcode

26. Control packet for memory read = x60
32 bits
Ver
IHL
Type of service
Total length
Identification
Flags
Fragment offset
TTL
Protocol
Header checksum
Source address
Destination address
Source port
Destination port
Length
Checksum
Opcode
Memory address

27. Executable to IP packet payload conversion flow
Issues to consider while writing a program for an embedded system that does not have an operating system (e.g. specifying a base address for the executable, etc)
Cross compiler tools for creating an executable
Program for converting an executable into an IP packet payload

28. Embedded Compilation Link script must be written w/ memory map in mind
Currently the link information is done on the LD command line
In general a separate link script is used

29. S/W Compilation Flow Uses LECCS Compiler System
GCC Based
Test PROMs used LEON compile scripts
General compile system developed uses DOS .bat compile script
Compile w/ GCC
Assemble w/ GAS
Link w/ LD
Convert to binary w/ OBJCOPY
Convert to IP w/ Forth program

30. An example C program int x = 1; int y = 2; int z; _start() { x = 5;
*(int*) 0x = x + y;
z = x - y;
while(1); }

31. Compile script sparc-rtems-gcc test.c -S
sparc-rtems-as test.s -o test.o
sparc-rtems-ld test.o -Ttext 0x0 -Tdata 0x1000 -Tbss 0x2000
sparc-rtems-objcopy a.out -O binary a.bin
\gforth0.6.2\gforth tobin.fs > \class\leon2\input_ip.dat

32. Conversion to IP s" a.bin" r/o open-file throw value fp
fp file-size throw drop value fsize
fsize allocate throw value buf
buf fsize fp read-file throw
fp close-file throw
hex
( print 32 bit big-endian word on little-endian processor )
: .BE
dup 04 rshift 0f and 0 1 ud.r dup 00 rshift 0f and 0 1 ud.r
dup 0c rshift 0f and 0 1 ud.r dup 08 rshift 0f and 0 1 ud.r
dup 14 rshift 0f and 0 1 ud.r dup 10 rshift 0f and 0 1 ud.r
dup 1c rshift 0f and 0 1 ud.r rshift 0f and 0 1 ud.r ;
( print 32 bit little-endian word on little-endian processor )
: .LE
dup 1c rshift 0f and 0 1 ud.r dup 18 rshift 0f and 0 1 ud.r
dup 04 rshift 0f and 0 1 ud.r rshift 0f and 0 1 ud.r

33. Conversion to IP (2) : dump-file fsize 4 / 0 do ." IPpacket" cr
LE cr
LE cr
LE cr
7f LE cr
807F0001 .LE cr
0000BEEF .LE cr
LE cr
LE cr
i cells .LE cr
buf i cells .BE cr
." wait_100" cr
loop
LE cr ;

34. Conversion to IP (3)
dump-file
buf free throw
bye

35. Interaction with LEON
Basic steps for “User” to interface with LEON/SRAM:
Wait for “READY” message
Load Program to SRAM
Send LEON “START” message
Wait for “DATA” message
Read results from SRAM

36. Sample program & Screen Shot
Sample Program (pseudo code)
x = 5
y = 6
y = x + y
RAM[0x4000_0000] = y
jmp “wait for next start”

37. Layered Protocol Wrappers
Questions?
Off-Chip
SRAM/SDRAM 1
SRAM/SDRAM 1
Controller
Leon Controller
Control Packet
Processor
(cpp)
(Modified MP3)
Alert Generator
(Modified MP3)
LEON
system
Layered Protocol Wrappers

38. Interface to SDRAM Controller
SDRAM must be accessed by User and Processor
FPX SDRAM Controller
Provides arbitrated access to SDRAM for up to three devices
Support for burst transfers up to 256 words

39. Interface to SDRAM Controller
Connecting to LEON controller
Simple State Machine to Perform Handshaking
Connecting to LEON Core
Replace existing SDRAM Controller
Build adapter to bridge FPX SDRAM Controller to LEON memory controller
Other Key Issues
Support for additional memory types
Changing the LEON address space