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Computer Science and Engineering Laboratory, 01.01.2011 Transport-triggered processors Jani Boutellier Computer Science and Engineering Laboratory This.

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Presentation on theme: "Computer Science and Engineering Laboratory, 01.01.2011 Transport-triggered processors Jani Boutellier Computer Science and Engineering Laboratory This."— Presentation transcript:

1 Computer Science and Engineering Laboratory, 01.01.2011 Transport-triggered processors Jani Boutellier Computer Science and Engineering Laboratory This work is licensed under a Creative Commons Attribution 3.0 Unported License: http://creativecommons.org/licenses/by/3.0/

2 Computer Science and Engineering Laboratory, 01.01.2011 What you will learn today What components does a TTA processor constitute of What TTA programs look like in machine code Basic optimization of TTA programs

3 Computer Science and Engineering Laboratory, 01.01.2011 Transport-triggered architecture Transport-triggered architecture (TTA) processors An evolution of the VLIW Only 1 instruction: move data  Compiler needs to do a lot of work Can be very efficient Easy to design, scalable

4 Computer Science and Engineering Laboratory, 01.01.2011 Transport-triggered architecture + * RFIO instr. unit Transport bus Function unit

5 Computer Science and Engineering Laboratory, 01.01.2011 TTAs do not have an instruction set, instead, the programmer (compiler) directly defines data transports between functional units RISC, CISC and VLIW processor move data between FUs through registers. A TTA can directly send data from one FU to another – possibility to save power Transport-triggered architecture

6 Computer Science and Engineering Laboratory, 01.01.2011 The general architecture of a TTA processor is very scalable: adding a new functional unit increases the complexity linearly The VLIW problem that TTA does not directly solve, is that of code density Transport-triggered architecture

7 Computer Science and Engineering Laboratory, 01.01.2011 TTA structure

8 Computer Science and Engineering Laboratory, 01.01.2011 TTA processors + * RFIO instr. unit Transport bus Function unit Socket

9 Computer Science and Engineering Laboratory, 01.01.2011 TTA processors * Function units connect to sockets through ports

10 Computer Science and Engineering Laboratory, 01.01.2011 TTA processors * Function units connect to sockets through ports Ports have either input or output direction This multiplier has two inputs for operands and one output for the result One of the inputs always triggers the FU

11 Computer Science and Engineering Laboratory, 01.01.2011 Computation example

12 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c);

13 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

14 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

15 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

16 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

17 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

18 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

19 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

20 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

21 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. unit a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside

22 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. mem a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside The program below is not optimal. What could be done better?

23 Computer Science and Engineering Laboratory, 01.01.2011 Computation example + * RFIO instr. mem a = READ_IO(); b = READ_IO(); c = a + b * b; WRITE_IO(c); mov IO(0) -> RF(a0); IO(0) is used to read data from outside mov IO(0) -> RF(a1); RF is a register file, to store data mov RF(a1) -> mul(0); mul(0) stores operand 1 of the multiplier mov RF(a1) -> mul(1); mul(1) stores operand 2 and triggers mov mul(2) -> RF(a2); mul(2) provides the multiplication result mov RF(a0) -> add(0); add(0) stores operand 1 of the adder mov RF(a2) -> add(1); b*b was stored to RF(a2) two lines before mov add(2) -> IO(1); IO(2) writes data to the outside The program below is not optimal. What could be done better? Circulating the data through RF is not necessary!

24 Computer Science and Engineering Laboratory, 01.01.2011 Multiple buses + * RFIO instr. unit This TTA processor has one bus. How would the functionality of the processor change if there would be a second bus?

25 Computer Science and Engineering Laboratory, 01.01.2011 Multiple buses + * RFIO instr. unit Every additional bus adds a possibility for another parallel transfer

26 Computer Science and Engineering Laboratory, 01.01.2011 Multi-bus example + * RFIO instr. mem Cycle 0Cycle 1Cycle 2Cycle 3 Bus 0 Bus 1 Bus 2 Bus 3

27 Computer Science and Engineering Laboratory, 01.01.2011 Multi-bus example + * RFIO instr. unit Cycle 0Cycle 1Cycle 2Cycle 3 Bus 0 mov IO(o1)  add(i1) Bus 1 mov RF(o1)  add(i2) Bus 2... Bus 3...

28 Computer Science and Engineering Laboratory, 01.01.2011 Multi-bus example + * RFIO instr. unit Cycle 0Cycle 1Cycle 2Cycle 3 Bus 0 mov IO(o1)  add(i1) Bus 1 mov RF(o1)  add(i2) Bus 2... mov add(o1)  mul(i1) Bus 3... mov mul(o1)  mul(i2)

29 Computer Science and Engineering Laboratory, 01.01.2011 Multi-bus example + * RFIO instr. unit Cycle 0Cycle 1Cycle 2Cycle 3 Bus 0 mov IO(o1)  add(i1) mov add(o1)  IO(i1) Bus 1 mov RF(o1)  add(i2) mov IO(o1)  add(i1) Bus 2... mov add(o1)  mul(i1)mov RF(o1)  add(i2) Bus 3... mov mul(o1)  mul(i2)...

30 Computer Science and Engineering Laboratory, 01.01.2011 Multi-bus example + * RFIO instr. unit Cycle 0Cycle 1Cycle 2Cycle 3 Bus 0 mov IO(o1)  add(i1) mov add(o1)  IO(i1)mov mul(o1)  IO(i1) Bus 1 mov RF(o1)  add(i2) mov IO(o1)  add(i1)mov add(o1)  RF(i1) Bus 2... mov add(o1)  mul(i1)mov RF(o1)  add(i2)... Bus 3... mov mul(o1)  mul(i2)... mov IO(o1)  add(i1)

31 Computer Science and Engineering Laboratory, 01.01.2011 Multiple buses + * RFIO instr. unit Going into detail, all sockets are actually not connected to every bus. Less connections means lower power consumption.

32 Computer Science and Engineering Laboratory, 01.01.2011 TTA instructions

33 Computer Science and Engineering Laboratory, 01.01.2011 TTA instructions + * RFIO instr. unit But how do the TTA instructions look like in binary format?

34 Computer Science and Engineering Laboratory, 01.01.2011 TTA instructions + * RFIO instr. unit 0000110100011... 00000011101010101000 168 bits for one instruction  42 bits for each bus

35 Computer Science and Engineering Laboratory, 01.01.2011 TTA instructions Each bus needs a 42 bit instruction each clock cycle. Where do the 42 bits come from? - How wide is an 8-bus TTA instruction?

36 Computer Science and Engineering Laboratory, 01.01.2011 TTA instructions Each bus needs a 42 bit instruction each clock cycle. Where do the 42 bits come from? -source port -destination port -opcode -guard bits -immediate values How wide is an 8-bus TTA instruction? 336b

37 Computer Science and Engineering Laboratory, 01.01.2011 TTA instructions Bus 1Bus 2Bus 3Bus 4Immed. guardsourcedest Instruction word

38 Computer Science and Engineering Laboratory, 01.01.2011 TTA instructions Very long instruction words (like 168 or 336 bits) require a lot of program memory space if the program is long To make the problem less severe, instruction compression techniques exist Instruction compression is based on a dictionary: compressed instructions are just index number that point to the full instruction in the dictionary

39 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization

40 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization The SW/HW designer of TTA processors must know the central issues about performance optimization How the algorithm works What resources the algorithm needs Understand how the C compiler works

41 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization The strength of TTA processors is that they can directly route data from one place to another, without obligatory register/memory stores Memory accesses are slow  the program should only access data memory when really necessary

42 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization The TTA processor for this code should have so much register space that memory accesses are not needed for this loop

43 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization By examining the assembly code (output of the C compiler), one can see if the loop has accesses the load-store unit (LSU). If it does, memory is accessed

44 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization By examining the assembly code (output of the C compiler), one can see if the loop has accesses the load-store unit (LSU). If it does, memory is accessed Bus 1Bus 2Bus 3Bus 4

45 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization The functionality of a signal processor must be balanced for high efficiency (low gate count, high throughput) FIR example: You start with a processor that has 1 multiplier and 1 adder. You want to make the processor 3 times faster.  if you make the processor have 3 multipliers, you probably also need 3 adders

46 Computer Science and Engineering Laboratory, 01.01.2011 Performance optimization Profiling tools are used to see if the processor is balanced Things to look for: –if there is a FU that is used much more often than others, it probably is a bottleneck –if there is a FU that has (almost) no accesses, it can be removed to save on gate count

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