1. Processor Power Management Overview

2. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM States
Sleep States
AMT States

3. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM State
Sleep States
Reset
Backup

4. Power Management under ACPI
Advanced Configuration and Power Management Interface
New concepts beyond APM
Fine granularity on CPU clock control
Multiple system sleeping states
Individual device management without H/W traps and timers
Thermal Management
Primary methodology for current power management.
Define Power States within the platform.
Lx States : Link States (for DMI and PEG)
Dx States : Device States
Cx States : CPU States.
Sx States : Sleep (System) States.
Mx States : ME (AMT)States.
Gx States : Global States.

5. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM States
Sleep States
Reset
Backup

6. Global system state Sleep / Hibernate Wake event
Individual devices can be in Dx and processor can be in Cx
G0/S0/C0: Full On
G0/S0/C1: Auto Halt
G0/S0/C2: Stop Grant
G0/S0/C3: Stop Clock
G0/S0/C4: Stop Clock with lower CPU voltage
G0/S0/C5 : Stop Clock with partial power off
G1/S1: Stop Grant
G1/S3: Suspend to ram (STR)
G1/S4: Suspend to Disk (STD)
G2/S5: Soft Off
G3 : no power at all ( no battery or the system is insufficient supply level to wake)
G0(Working State)
- System is running
- Power is on
Sleep /
Hibernate
Wake event
G1(Sleeping State)
No System Traffic
MCH, ICH and CPU off
OS initiate Power off
PWR plug in &
AFTERG3_EN=0
G2(Soft Off)
- No System Traffic
- System is off
- Small part of ICH remains on to accept
wake up event.
G3(Mech. Off)
System is unplugged
RTC battery continues
to supply power to RTC
PWR plug in &
AFTERG3_EN=1
Global system state

7. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM States
Sleep States
Reset
Backup

8. Device States : General
D0 Fully-On
This state is assumed to be the highest level of power consumption. The device is completely active.
D1 - D2
Optional. Expected to save more power and preserve less device context than D0. D2 save more power than D1 but the latency is high.
D3 Off
- Power has been fully removed from the device. The device context is lost when this state is entered, so the OS software will reinitialize.

9. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM States
Sleep States
Reset
Backup

10. CPU States : General C0 Processor Power State
Normal state. While the processor is in this state, it executes instructions.
C1-C5 Processor Power State
Non executing power state.
The deeper the C state, the lower the power consumed by the processor in that state.
Processor power in C1 is higher than the processor power in C4.
The deeper the C state, the higher the entry and exit latency of that state
Entry/exit latency of C4 is higher than that of C1

11. Intel CPU States State Entry Method Bus Masters Allowed Notes
Break Event C0 --
All
CPU is executing instructions C1
AutoHalt inst.
Entered by CPU when it has nothing to do
Transparent to chipset
Interrupt events (SMI, SCI..) C2
Level 2 I/O read (LvL2)
ICH asserts STPCLK#
MCH may dynamically assert SLP#
Most CPU I/F signals are latched
Interrupt (Key stroke, Mouse Movement, RTC) C3
Level 3 I/O read (LvL3)
only isoc*
ICH asserts STPCLK#, DPSLP#, STP_CPU#
MCH or ICH asserts SLP#
Bus master snoop request
Unmasked interrupt: SMI#, NMI#
CPU break (FERR#) C4
Level 4 I/O read (LvL4)
or C4onC3
ICH asserts STPCLK#, DPSLP#, STP_CPU#, DPRSTP#, DPRSLPVR

12. Intel CPU States State Entry Method Bus Masters Allowed Notes Break
C5/C6
Level 5/6 I/O read (LvL5/LvL6)
All
CPU flushes cache prior to entry, so snoops aren’t necessary. CPU will be [almost] fully powered down.
ICH asserts STPCLK#, DPSLP#, STP_CPU#, DPRSTP#, DPRSLPVR, #PMSYNC
MCH or ICH asserts SLP#
Most CPU I/F signals are latched
Same pins as C4, but different timings and abbreviated messaging
Interrupt events

13. Intel® Deep Power Down Technology (C6)
Flexible C-States to Select Idle Power Level vs. Responsiveness

14. C2 Entry/Exit Sequences
Note:
“M-I link” is DMI.
“SG” message on “M-I link” should be “Req-C2”

15. C3 Entry Sequences

16. C3 Exit Sequences

17. C4 Entry Sequences

18. C4 Exit Sequences

19. C5/C6 Entry Sequences

20. C5/C6 Exit Sequences

21. NHM CPU States NHM supports C0, C1, C1E, C3, C6 and C7.
C7 is identical to C6 at core level but different Uncore power optimization.
C7 is an overall package state where all cores have lost their registers, last level cache is at its minimum voltage but uncore is still in retention voltage
On NHM, STPCLK#, SLP# and DPSLP# signals are removed due to platform change and CSI bus interface.
Not all package C-state will be supported on all versions of NHM like Uncore power reduction features on C3 and lower power states maybe fused off in desktop or server parts.

22. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM State
Sleep States Reset
Common Questions

23. Link PM States L0 – Active state
TLP(Transaction Layer Packet)’s and DLLP(Data Link Layer Packet)’s are permitted
L0s – Low resume latency, energy saving “standby” state:
no TLP/DLLP during L0s state
quick entry/exit, exit in the order of 100 ns for Intel chipset
L0s is single-directional. A transmitter can initiate L0s without the other port initiating L0s.
Main power and clocks remain.
Chipset gates some internal logic.
L1 – lower power standby state – Higher latency PM state:
Downstream port initiates when the device power state is programmed to non D0 state(D3)
no TLP/DLLP during L1 state.
Exit in order of micro seconds.

24. Link PM States (Contd..)
L2/3 ready – Staging point for L2/L3 – Required for PCIe PM before entering L2 or L3 state, this is not a real link state, it is just a phase requiring protocol handshake before entering L2 or L3.
A device must be in D3 state before entering L2/3 ready
System will place link L2/3 ready state before entering S3/S4/S5.
L2 – Auxiliary powered Link deep energy state. L2 is optionally supported.
Main power and clks are removed
the device has aux power to perform link reactivation through beacon, WAKE#, PME context and detection logic.
L3 – Link off state. Zero power state.

25. Link PM States (Contd..) Summary of Link PM States:
L-State Description
Used By SW Directed PM
Used By ASPM L0
Fully Active
Yes(D0)
Yes (D0)
L0s
Standby No L1
Lower Power Standby
Yes(D1-D3hot)
L23 Ready
Staging point for power removal
Yes (links to PME_turn_off message ) L2
Low Power Sleep State
Yes L3
Off (No Vaux)
N/A
Ldn
Transitional State before L0

26. Link PM States (Contd..) ASPM Control: Allows Hardware controlled PCIe dynamic link power reduction.
Value
Description
00 – Disabled
Port must not bring a Link into L0s state.
Port must not initiate a PM_active_State_Request_L1 DLLP to other end of the link
Port receiving a L1 request from other agent must respond with negative acknowledgement.
01b – L0s Entry Enabled
Port must bring a Link into L0s state when all conditions are met.
10b – L1 Entry Enabled
Port’s transmitter must not bring a Link into L0s state.
Port may issue a PM_active_State_Request_L1 DLLP to other end of the link
Port receiving a L1 request from other agent must respond with positive acknowledgement.

27. Link PM States (Contd..) ASPM Control:
Value
Description
11b – L0s and L1 Entry Enabled
Port’s transmitter must bring a Link into L0s state.
Port may issue a PM_active_State_Request_L1 DLLP to other end of the link
Port receiving a L1 request from other agent must respond with positive acknowledgement.

28. Link PM States (Contd..) Relationship between Link and Device PM State.
Device State
Permissible Interconnect Link State D0
L0, L0s, L1 (ASPM) D1 L1 D2 L2
D3hot
L1, L2/L3 ready
D3cold
L2, L3

29. System and DMI Link Power States
System States
CPU State
Description
Link State
SW Controlled S0 C0
Fully Operation. Opportunistic Link Active State
L0/L0 s/L1
N/A C1
CPU Auto Halt
Yes C2
CPU Stop Clock C3
Deep Sleep: CPU’s clock halted via STP_CPU# assertion. MCH and ICH still being clocked

30. System and DMI Link Power States
System States
CPU State
Description
Link State
SW Controlled S0 C4
Deeper Sleep: CPU’s clock halted via STP_CPU# assertion and CPU’s voltage lowered.
L0/L0 s/L1
Yes
S1/S1D C2
S1D same as C2
S3/S4/ S5
N/A
STR/STD/Off L3

31. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM State
Sleep States
Reset
Backup

32. Sleep States – User Point of View
Common Names
Description S1
Stand By,
Powered on Suspend (refers to S1M state – last supported on ICH5)
Entered by pressing sleep button, closing lid, system idle, etc. System appears mostly off (LED’s may indicate Stand By). Common wake events include power button, sleep button, mouse movement, modem ring, etc. System wakes quickly and all programs are still running. S2
Not supported by Intel chipsets S3
Suspend to RAM
To user, appears the same as S1, but in mobile system the battery can maintain S3 much longer. Wake will take longer than S1, but still very fast.
S3 is “suspend” when pressing Fn + F4. S4
Hibernate,
Suspend to Disk
Entered by user direction or system idle. System appears off. Most common wake event would be power button, but all others are still possible. System takes longer to wake than S3, but all programs are still running.
S4 is “hibernate” when pressing Fn + F12. S5
Shut Down,
Soft Off
Entered by user direction (Start -> Shut Down). Very similar to S4, but a full boot occurs on wake (no programs remain running from previous S0). Desktop must stay plugged in, laptop must have charged battery, otherwise platform is in G3.

33. Sleep State Entry Sequence
STPCLK#
DMI
CPUSLP#
SUS_STAT#
PLTRST#
SLP_S3#
PWROK#
SLP_S4#
SLP_S5#
REQ - C2 Go
Ack S3
t53c
t53b
t56 +t58
t59
t60 (for S3
Cold only)
t61
t62 S0 S1 S4 S5
t55
L2/ L3

34. Sleep State Exit Sequence

35. Agenda Introduction Overview of all power states Global States
Device States
CPU States
PCIe Link PM State
Sleep States Reset
AMT Status

36. ME impact on Sleep States

40. Thank You