# Floating Point Unit. Floating Point Unit ( FPU ) There are eight registers, namely ST(0), ST(1), ST(2), …, ST(7). They are maintained as a stack.

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Floating Point Unit

Floating Point Unit ( FPU ) There are eight registers, namely ST(0), ST(1), ST(2), …, ST(7). They are maintained as a stack.

Floating Point Unit ( FPU ) The top element of the stack is always named as ST(0). For example,.data v1REAL8 1.23 v2REAL8 6.3 v3REAL8 7.9.code finit fld v1 fld v2 fld v3 finit finitfinitfinit fld v1fld v1fld v1fld v1 fld v2fld v2fld v2fld v2 fld v3fld v3fld v3fld v3 1.23 7.9 6.3 1.23 6.3 1.23 ST(0) ST(1) ST(0) ST(1) ST(2)

Generate a series: 1, 2, 3, 4, …, (1) S n+1 = S n + 1 (2) S 1 = 1 Store the elements in an array. We need to initialize the first element and then apply (1)..data v REAL8100 DUP(?) ONEREAL81.0 numDWORD10.code mov edi, 0 finit fld ONE fst v[edi] mov ecx, num dec ecx cmp ecx, 0;signed jle Ldone L1: finit fld ONE fld v[edi] fadd ST(0), ST(1) add edi, 8 fst v[edi] loop L1 Ldone:

Generate Fibonacci series (numbers) (1) S n+2 = S n+1 + S n (2) S 0 = 1, S 1 = 1 (seed values) Generate the first m numbers.

Generate Fibonacci series (numbers) (1) S n+2 = S n+1 + S n (2) S 0 = 0, S 1 = 1 (seed values) Generate the first m numbers..code SREAL80.0, 1.0, 100 DUP(?) mDWORD10.code mov edi, 2*8 mov esi, 0 mov ecx, m sub ecx, 2 cmp ecx, 0 jle Ldone;signed L1: finit fld S[esi] fld S[esi+8] fadd ST(0), ST(1) fst S[edi] add edi, 8 add esi, 8 loop L1 Ldone:

Conditional jumps cmp eax, a ja L1; eax> a; unsigned comparison jb L1; eax < a jae L1; eax >= a je L1; eax == a jl, jg; signed comparison

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