1. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 1 Intel IA-32 vs Motorola 68000

2. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 2 Major Differences Addressing: –Motorola: 24-bit addressing –Intel: 32-bit addressing Memory Access: –Motorola: Big-endian Memory Access –Intel: Little-endian memory access Instruction Format: –Motorola: mnemonic source, dest –Intel: mnemonic dest, source Registers –Motorola: 16 registers (8 address, 8 data) –Intel: 8 registers (some with special purpose) Stack –Motorola: Entries can be words or double words –Intel: Entries are all double words

3. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 3 Registers 4 32-bit data registers –EAX, EBX, ECX, EDX 4 32-bit index registers –EPB, ESP, ESI, EDI 6 16-bit segment registers –CS, DS, SS, ES, FS, GS 1 32-bit EIP 1 32-bit EFLAGS

4. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 4 Data Registers EAX/R0 (accumulator) – for arithmetic operations EBX/R3 (base) – holds address of a procedure or variable; also for arithmetic operations and data movement. ECX/R1 (counter) – for repeating or looping instructions EDX/R2 (data) – for I/O; for multiply and divide operations Can be used as general purpose registers. The low order byte of EAX can be accessed by AL, the next higher order byte can be accessed by AH, and the entire low order word can be accessed by AX.

5. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 5 Index Registers ESP/R4 (stack pointer) – offset from the top of the stack EBP/R5 (base pointer) – base for the stack (frame pointer) ESI/R6 (source index) – for string movement. Address of source string is in ESI. EDI/R7 (dest index) – for string movement. The destination address is in EDI. Can be used as general purpose registers (except R4, R5) Can access first (rightmost) word with SP, BP, SI, DI, respectively.

6. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 6 Segment Registers CS (code segment) – base location of executable instructions DS (data segment) – default location for variables SS (stack segment) – base location for the stack ES, FS, GS (extra segment) – additional base location for memory variables

7. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 7 EIP and EFLAGS Registers Motorola Program Counter (PC) –EIP – Extended (32-bit) Instruction Pointer Motorola Status Register (SR) –EFLAGS – Extended Flags SF – sign ZF – zero OF – overflow CF – carry IF – interrupt (can interrupts occur) TF – trap (same as Motorola trace bit)

8. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 8 Constants and Expressions Decimal (default) –Motorola: 123 –Intel: 123 Binary – trailing ‘b’ –Motorola: %1010 –Intel: 1010b Hexadecimal – trailing ‘h’ (and must start with number) –Motorola: $AF01 –Intel: 0AF01h Octal – trailing ‘o’ or ‘q’ –Motorola: @123 –Intel: 123o or 123q Strings –‘hello’ or “hello”

9. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 9 Directives and Comments Motorola EQU –EQU – assigns a name to a string or numeric constant Motorola DC –DB – define byte (8 bits) –DW – define word (2 bytes) –DD – define double word (4 bytes / 2 words) Motorola DS –Use DB, DW, or DD with ? for value Intel Only –Equal-sign – symbolic constant ‘;’ indicate comments, as in Motorola

10. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 10 Directives and Comments Define starting places for code and data. –.code –.data –.stack 4096 – reserve 4096 bytes for the stack

11. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 11 Directives: Example Motorola ; Data and Constants CHAR1DC.B ‘A’ CHAR2 DC.B +127 CHAR3 DS.B 1 LIST DS.B 10, 20, 30 Intel.data CHAR1 DB ‘A’ CHAR2 DB +127 CHAR3 DB ? LIST DB 10, 20, 30

12. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 12 Instruction Format Mnemonic dest,source –ADD Motorola: ADD source, dest Intel: ADD dest, source RTL: dest <- dest + source –MOVE Motorola: MOVE source, dest Intel: MOV dest, source RTL: dest <- source General Rules –Source can be memory, register or constant –Destination can be memory or non-segment register –Only one of source and destination can be memory –Source and destination must be same size

13. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 13 Addressing Modes Motorola Immediate Mode –Intel Immediate mode –Operand = Value Motorola Absolute Long Mode –Intel Direct mode – 32 bit address –Operand = Location Motorola Address/Data Register Direct –Intel Register mode –Operand = Reg Motorola Register Indirect –Intel Register Indirect –Operand = [Reg] Motorola Indexed Basic Mode –Intel Base with Displacement mode –Operand = [Reg + Displacement] Motorola Autoincrement/Autodecrement –No equivalent in Intel

14. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 14 Flow Control Compare –Motorola: CMP –Intel: CMP Branch Always –Motorola: BRA –Intel: JMP Branch Greater/Less Than –Motorola: BGT/BLT –Intel: JG/JL Branch Greater/Less Than or Equal To –Motorola: BGE/BLE –Intel: JGE/JLE As in Motorola, branching instructions (Jump) branch to a displacement added to the program counter (instruction pointer IP)

15. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 15 Example: Summing an Array INTEL IA-32 Assembly Language LEA EBX, ARRAY; Initialize base (EBX) register with ARRAY MOV ECX, N; Initialize counter (ECX) register with N MOV EAX, 0; Clear accumulator (EAX) MOV EDI, 0; Clear index (EDI) LOOP:ADD EAX, [EBX + EDI *4]; Add next number into accumulator (EAX) INC EDI; Increment index register (EDI) DEC ECX; Decrement counter register (ECX) JG LOOP; Branch if [ECX > 0] MOV SUM, EAX; Store sum (EAX) in memory (SUM) MOTOROLA 68000 Assembly Language MOVE.L N, D1; Initialize counter (D1) MOVEA.L #ARRAY, A2; Initialize base (A2) with ARRAY CLR.L D0; Clear accumulator (D0) LOOPADD.W (A2)+, D0; Add next number into accumulator, increment A2 SUBQ.L #1, D1; Decrement counter register (D1) BGT LOOP; Branch if [D1 > 0] MOVE.L D0, SUM; Store sum (D0) in memory (SUM)

16. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 16 The Stack All entries in the stack are double words (4 bytes) Pushing an item onto the stack –Motorola: MOVE itemSrc, -(SP) –Intel: PUSH itemSrc Popping an item from the stack –Motorola: MOVE +(SP), itemDest –Intel: POP itemDest PUSH and POP implicitly use ESP for current stack pointer

17. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 17 Subroutines Calling a Subroutine –Motorola: BSR/JSR sub –Intel: CALL sub Return from Subroutine –Motorola: RTS –Intel: RET Storing Multiple Registers on the stack –Motorola: MMOVE D3-D5/A2, -(SP) –Intel: PUSHAD

18. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 18 Subroutines Example INTEL IA-32 Assembly Language PUSH OFFSET ARRAY; Push address of ARRAY onto stack PUSH N; Push number of elements onto stack CALL LADD; Branch to subroutine LADD (list add) ADD ESP,4; Clean stack POP SUM; Store returned sum in memory (SUM) LADD:PUSHAD MOV EDI, 0; Clear index (EDI) MOV EAX, 0; Clear accumulator (EAX) MOV EBX,[ESP+44]; Load ARRAY address into EBX MOV ECX,[ESP+40]; Load N into ECX LOOP:ADD EAX, [EBX + EDI *4]; Add next number into accumulator (EAX) INC EDI; Increment index register (EDI) DEC ECX; Decrement counter register (ECX) JG LOOP; Branch if [ECX > 0] MOV [ESP+44],EAX; Overwrite ARRAY in stack with sum POPAD RET

19. CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 19 References HVZ: Chapter 3.16 – 3.24 HVZ: Appendix D Art of Assembly - http://webster.cs.ucr.edu/http://webster.cs.ucr.edu/ Usenet: comp.lang.asm.x86