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C2 Part 4: VLSI CAD Tools Problems and Algorithms Marcelo Johann EAMTA 2006

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EAMTA Marcelo Johann - C21.2Outline THIRD PART Layout Compaction Logic Synthesis, BDDs Technology Mapping Simmulation vs Formal Verification Voltage Drop by Random Walks FOURTH PART High-Level Synthesis CDFG, Allocation, Scheduling, Generation

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EAMTA Marcelo Johann - C21.3 Function representations Truth Tables Lists the output for every input combination For n variables, 2 n lines Formulas F=x1.x2.~x5 + ~x3(x2.x4.x5 + ~x2) + x2.x3 Not Canonical in general, canonical is large BDDs A graph that packs a truth table Average sized, powerful representation

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EAMTA Marcelo Johann - C21.4BDDs Source: Wikipedia

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EAMTA Marcelo Johann - C21.5 BDD - good ordering BDD graph for the Boolean formula x1 * x2 + x3 * x4 + x5 * x6 + x7 * x8 using a good variable ordering

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EAMTA Marcelo Johann - C21.6 BDD - bad ordering BDD graph for the Boolean formula x1 * x2 + x3 * x4 + x5 * x6 + x7 * x8 using a bad variable ordering

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EAMTA Marcelo Johann - C21.7 Random Walks

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EAMTA Marcelo Johann - C21.8 Random Walks

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EAMTA Marcelo Johann - C21.9 IR Drop

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EAMTA Marcelo Johann - C21.10 Random Walk

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EAMTA Marcelo Johann - C21.11 The Algorithm Initialize Compute conductance, p x,i, m x For each node in the circuit Loop n times according to accuracy Loop until reaching Supply –Add this node’s cost –Random select the next move Make this node a new supply Print the result

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EAMTA Marcelo Johann - C21.12Accuracy VDD nodes GND nodes 1.2V Linux 2.8GHz CPU Delta controls error such that 99% of the nodes have less then Error Margin

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EAMTA Marcelo Johann - C21.13 VLSI System Design Part V : High-Level Synthesis Lecturer : Tsuyoshi Isshiki VLSI Design and Education Center, The University of Tokyo Dept. Communication and Integrated Systems, Tokyo Institute of Technology Jump to…

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C2: VLSI CAD Tools Problems and Algorithms EAMTA 2006 Marcelo Johann Thank you!

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