2. Chapter 3 โพรเซสเซอร์และการทำงาน The Processing Unit
Fundamental of Computer Architecture

3. เนื้อหา
นิยาม และคำศัพท์ที่ควรรู้เกี่ยวกับไมโครโพรเซสเซอร์และ ไมโครคอมพิวเตอร์
ประวัติความเป็นมาของไมโครโพรเซสเซอร์
ข้อดีข้อเสียของไมโครโพรเซสเซอร์
ข้อพิจารณาในการเลือกใช้ไมโครโพรเซสเซอร์
Fundamental of Computer Architecture

4. Computer BUS A group of wires that connects several devices
Three types of Bus
Address bus
Data bus
Control bus
Fundamental of Computer Architecture

5. Address bus
Used to specify memory location that the cpu want to access(read/write)
n-bit address bus provides 2n addresses
For Example
MCS bit address bus -> 216 = 16 Kbyte of memory
bit address bus -> 220 = 1 Mbyte of memory
Pentium 32-bit address bus -> 232 = 4 Gbyte of memory
Fundamental of Computer Architecture

6. Databus Used to sent data between CPU and peripheral(memory, i/o)
The more bit of data bus, the more speed achieved
For Example
MCS bit data bus
bit data bus
Pentium 64-bit data bus
Fundamental of Computer Architecture

7. BUS
Fundamental of Computer Architecture

8. CPU : Basic operations
Fetch : Read the instructions and data from memory
Execute : perform the desired operation and write the result into the memory or registers
Fundamental of Computer Architecture

9. FETCH
Fundamental of Computer Architecture

10. 240-208 Fundamental of Computer Architecture

11. Terminology IR : Instruction Register MAR : Memory Address Register
Fundamental of Computer Architecture

12. Instructions of CPU There are 4 types of instructions
1. Data transfer between memory and CPU registers
2. Arithmetic and Logic Operations on data
3. Program Sequencing and Control
4. I/O transfer
Fundamental of Computer Architecture

13. Basic instruction types : three address instruction
D = A+B+C
LOAD R0,[10000]
LOAD R1,[10001]
ADD R2, R0, R1
LOAD R0,[10002]
ADD R1, R0,R2
STORE [10003],R1
Note ADD R2,R0,R1 means R2 = R0+R1
Fundamental of Computer Architecture

14. Basic instruction types : two address instruction
D = A+B+C
LOAD R0,[10000]
LOAD R1,[10001]
ADD R0,R1
LOAD R2,[10002]
ADD R0,R2
STORE [10003],R0
Note ADD R0,R1 means R0 = R0+R1
Fundamental of Computer Architecture

15. Basic instruction types : one address instruction
D = A+B+C
LOAD [10000]
ADD [10001]
ADD [10002]
STORE [10003]
Note ADD [10001] means Acc = Acc + [10001]
Fundamental of Computer Architecture

16. CPU registers General purpose registers Special purpose register
R0,R1…Rn
A,B, C,….
Special purpose register PC SP
Accumulator
Flag or Condition code
Fundamental of Computer Architecture

17. PC :Program Counter register
Used to keep the next address of memory that CPU want to access
PC and address-bus have the same size
Fundamental of Computer Architecture

18. PC :Program Counter (continued)
Fundamental of Computer Architecture

19. PC :Program Counter (continued)
Fundamental of Computer Architecture

20. PC :Program Counter (continued)
Fundamental of Computer Architecture

21. PC :Program Counter (continued)
Fundamental of Computer Architecture

22. PC :Program Counter (continued)
Fundamental of Computer Architecture

23. PC :Program Counter (continued)
Fundamental of Computer Architecture

24. Branching [25000] = [10000]+[10002]+[10003]+….+[24999]
LOC35000: LOAD R0,#0
LOAD R1,#14999
LOAD R3,#10000
LOC35003: LOAD R2,[R3]
ADD R0, R2
INC R3
DEC R1
Branch_NZ LOC35003
STORE [R3],R0
Fundamental of Computer Architecture

25. Flag or Condition code Register
keep the status after perform arithmetic and logic operation
Example: Flags of CPU z80
Fundamental of Computer Architecture

26. Addressing modes of CPU
Immediate #value load R0,#00001
Register Ri load R0,R1
Direct(absolute) [mem_loc] load R0,[100000]
Register indirect [Ri] load R0,[R1]
Relative X[PC]
Index
Fundamental of Computer Architecture

27. Immediate addressing load R1,#00001
Fundamental of Computer Architecture

28. Direct addressing LOAD R1,[1200H]
Fundamental of Computer Architecture

29. Register indirect load R0,[R1]
Fundamental of Computer Architecture

30. Index addressing Use index register Effective address = X + [Ri]
When X = offset (or displacement)
Ri = index register or Base register
Fundamental of Computer Architecture

31. Index addressing Offset is given as a constant
Fundamental of Computer Architecture

32. Index addressing Offset is in the index register
Fundamental of Computer Architecture

33. Example1 : Transfering bytes of data
Copy values in memory location 1000h-1400h to location 2000h-2400h (1024 byte)
Fundamental of Computer Architecture

34. Example1 : Transfering bytes of data
STRT: LD R0,#1000H
LD R1,#2000H
LD R3,#1024
LOC_A: LD R4, [R0]
STORE [R1], R4
INC R0
INC R1
DEC R3
BRANCH>0 LOC_A
CALL PRINTF
Fundamental of Computer Architecture

35. Example2: Unsigned Multiplication by Repeated Addition
Multiply 8-bit unsigned number
C = A * B
Fundamental of Computer Architecture

36. Example2: Unsigned Multiplication by Repeated Addition
Fundamental of Computer Architecture

37. Example2: Unsigned Multiplication by Repeated Addition
STRT : LOAD R1,#0
LOAD R3, [mem_loc_A]
LOAD R2, [mem_loc_B]
LOOP: ADD R1,R3
DEC R2
BRANCH>0 LOOP
STORE [mem_loc_C],R1
CALL PRINTF
Fundamental of Computer Architecture

38. Example2: Unsigned Multiplication by Repeated Addition
Problem of the program in page 37
If B = 0 then the result is A , not 0
How to remedy the problem
Fundamental of Computer Architecture

39. Example2: Unsigned Multiplication by Repeated Addition
STRT : LOAD R1,#0
LOAD R3, [mem_loc_A]
LOAD R2, [mem_loc_B]
Compare R2,#0
Branch_Z STR
LOOP: ADD R1,R3
DEC R2
Branch>0 LOOP
STR: STORE [mem_loc_C],R1
Fundamental of Computer Architecture

40. Example3: if-then-else
if (mem_loc_a == 5)
mem_loc_b++;
else
mem_loc_b = mem_loc_a + mem_loc_b;
Fundamental of Computer Architecture

41. Example3: if-then-else
Load R1,[mem_loc_a]
Load R2,[mem_loc_b]
Compare r1,#5
Branch_NZ b_p_a
inc r2
branch stre
b_p_a: Add r2,r1
stre: Store [mem_loc_a],r1
Store [mem_loc_b],r2
Fundamental of Computer Architecture

42. Example4: checking greater-than
if (mem_loc_a > 5)
mem_loc_b++;
else
mem_loc_b = mem_loc_a + mem_loc_b;
Fundamental of Computer Architecture

43. Example4: checking greater-than
Load R1,[mem_loc_a]
Load R2,[mem_loc_b]
compare r1,#5
branch_z equ_g_5 ;equal 5
branch_M equ_g_5 ;M= minus
inc r2
branch stre
equ_g_5: Add r2,r1
stre: Store [mem_loc_a],r1
Store [mem_loc_b],r2
Fundamental of Computer Architecture

44. Example4: checking greater-than
Load R1,[mem_loc_a]
Load R2,[mem_loc_b]
sub r1,#5
branch>0 gt_5
Add r2,r1
branch stre
gt_5: inc r2
stre: Store [mem_loc_a],r1
Store [mem_loc_b],r2
Fundamental of Computer Architecture

45. Basic processing unit the structure of simple CPU
How the internal parts of CPU work
How to design the simple processor
Datapath
Control Unit
Fundamental of Computer Architecture

46. Inside simple CPU with Single-bus Datapath
Fundamental of Computer Architecture

47. Perform instruction ADD R1,R2
MAR <= PC
ADDRESS_BUS <= MAR, read
MDR <= MEMORY[MAR]
IR <= MDR
Z <= PC + 4
PC <= Z
Y <= R1
Z <= Y + R2
R2 <= Z
Fetch phase
Execution phase
Fundamental of Computer Architecture

48. Perform instruction ADD R1,R2
Active Signals
MAR <= PC PCout, MARin
ADDRESS_BUS <= MAR,read read
MDR <= MEMORY[MAR] MDRinE, WMFC
IR <= MDR MDRout,IRin
Z <= PC + 4 PCout, MUX_sel4, Add,Zin
PC <= Z Zout,PCin
Y <= R1 Yin, R1out
Z <= Y + R2 R2out, MUX_selY, Add, Zin
R2 <= Z Zout, R2in
Fundamental of Computer Architecture

49. How to modify FETCH operation to be faster
MAR <= PC
ADDRESS_BUS <= MAR, Read
MDR <= MEMORY[MAR], WMFC
IR <= MDR
Z <= PC + 4
PC <= Z
MAR <= PC, Read, Z <= PC+4 , MDR <= MEMORY[MAR]
PC <= Z, WMFC
IR <= MDR
Fundamental of Computer Architecture

50. Modified FETCH operation
Active Signals
MAR <= PC, Read, Z <= PC+4 , MDR <= MEMORY[MAR]
PC <= Z, WMFC
IR <= MDR
PCout, MARin, Read, Mux_sel4, Add, Zin
Zout, PCin, Yin, WMFC
MDRout, IRin
Fundamental of Computer Architecture

51. Perform instruction load R1,[mem_locA]
MAR <= PC, Read, Z <= PC+4 , MDR <= MEMORY[MAR]
PC <= Z, WMFC
IR <= MDR
MAR <= & IR24..0
ADDRESS_BUS <= MAR
MDR <= MEMORY[MAR]
R1 <= MDR
Fetch phase
Execution phase
Fundamental of Computer Architecture

52. Three-bus organization
Fundamental of Computer Architecture

53. Perform Instruction ADD R6,R5, R4
Step Action
1 PCout, R=B, MARin, Read, incPC
2 WMFC, MDRin_from_databus
3 MDRout_busB, R= B, IRin
4 R4out_busB, R5out_busA, Add, R6in, End
Fundamental of Computer Architecture

54. Control Units 2 types of Control units Hardwired Microprogrammed
Fundamental of Computer Architecture

55. Control sequence for instruction ADD R1,(R3)
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, PCin, Yin, WMFC
3 MDRout, IRin
4 R3out, MARin, Read
5 R1out, Yin, WMFC
6 MDRout, SelectY, Add, Zin
7 Zout, R1in, End
Fundamental of Computer Architecture

56. Control sequence for instruction Branch
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, PCin, Yin, WMFC
3 MDRout, IRin
4 Offset-field-of-IRout, ADD, Zin
5 Zout, PCin, End
Fundamental of Computer Architecture

57. Control sequence for instruction Branch<0
Step Action
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, PCin, Yin, WMFC
3 MDRout, IRin
4 Offset-field-of-IRout, ADD, Zin, if N=0 then End
5 Zout, PCin, End
Fundamental of Computer Architecture

58. Hardwired Control Unit
Fundamental of Computer Architecture

59. Control Unit organization
Fundamental of Computer Architecture

60. Zin and END control signals
Zin = T1 + (T6ADD) + (T4  BR)+…..
End = (T7 ADD) + (T5 BR) + (((T5 N)+(T4 N)) BRN)+....
Note
BR = Branch instruction
BRN = Branch<0 instruction
N = Negative flag
Fundamental of Computer Architecture

61. Generation of Zin control signal
Fundamental of Computer Architecture

62. Generation of END control signal
Fundamental of Computer Architecture

63. Microprogrammed control unit
Fundamental of Computer Architecture

64. “Control words” stored in “Control Store”
From Figure 7.15 page 430 of “Computer Organization”, 5th edition, Carl Hamacher, McGraw Hill
Fundamental of Computer Architecture

65. จบ บทที่ 3
Fundamental of Computer Architecture