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Fundamental of Computer Architecture By Panyayot Chaikan 240-208 November 01, 2003.

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Presentation on theme: "Fundamental of Computer Architecture By Panyayot Chaikan 240-208 November 01, 2003."— Presentation transcript:

1 Fundamental of Computer Architecture By Panyayot Chaikan November 01, 2003

2 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Chapter 3 โพรเซสเซอร์และการ ทำงาน The Processing Unit

3 Chapter 3 - The Processing Unit Fundamental of Computer Architecture เนื้อหา นิยาม และคำศัพท์ที่ควรรู้เกี่ยวกับไมโคร โพรเซสเซอร์และ ไมโครคอมพิวเตอร์ ประวัติความเป็นมาของไมโครโพรเซสเซอร์ ข้อดีข้อเสียของไมโครโพรเซสเซอร์ ข้อพิจารณาในการเลือกใช้ไมโครโพรเซสเซอร์

4 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Computer BUS  A group of wires that connects several devices  Three types of Bus  Address bus  Data bus  Control bus

5 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Address bus  Used to specify memory location that the cpu want to access(read/write)  n-bit address bus provides 2 n addresses  For Example  MCS bit address bus-> 2 16 = 16 Kbyte of memory  bit address bus -> 2 20 = 1 Mbyte of memory  Pentium 32-bit address bus -> 2 32 = 4 Gbyte of memory

6 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Databus  Used to sent data between CPU and peripheral(memory, i/o)  The more bit of data bus, the more speed achieved  For Example  MCS-51 8-bit data bus  bit data bus  Pentium 64-bit data bus

7 Chapter 3 - The Processing Unit Fundamental of Computer Architecture BUS

8 Chapter 3 - The Processing Unit Fundamental of Computer Architecture CPU : Basic operations  Fetch : Read the instructions and data from memory  Execute : perform the desired operation and write the result into the memory or registers

9 Chapter 3 - The Processing Unit Fundamental of Computer Architecture FETCH

10 Chapter 3 - The Processing Unit Fundamental of Computer Architecture

11 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Terminology  IR : Instruction Register  MAR : Memory Address Register

12 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Instructions of CPU  There are 4 types of instructions 1. Data transfer between memory and CPU registers 2. Arithmetic and Logic Operations on data 3. Program Sequencing and Control 4. I/O transfer

13 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : three address instruction  LOAD R0,[10000]  LOAD R1,[10001]  ADD R2, R0, R1  LOAD R0,[10002]  ADD R1, R0,R2  STORE [10003],R1 D = A+B+C Note ADD R2,R0,R1 means R2 = R0+R1

14 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : two address instruction  LOAD R0,[10000]  LOAD R1,[10001]  ADD R0,R1  LOAD R2,[10002]  ADD R0,R2  STORE [10003],R0 D = A+B+C Note ADD R0,R1 means R0 = R0+R1

15 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic instruction types : one address instruction  LOAD [10000]  ADD [10001]  ADD [10002]  STORE [10003] D = A+B+C Note ADD [10001] means Acc = Acc + [10001]

16 Chapter 3 - The Processing Unit Fundamental of Computer Architecture CPU registers  General purpose registers  R0,R1…Rn  A,B, C,….  Special purpose register  PC  SP  Accumulator  Flag or Condition code

17 Chapter 3 - The Processing Unit Fundamental of Computer Architecture PC :Program Counter register  Used to keep the next address of memory that CPU want to access  PC and address-bus have the same size

18 Chapter 3 - The Processing Unit Fundamental of Computer Architecture PC :Program Counter (continued)

19 Chapter 3 - The Processing Unit Fundamental of Computer Architecture PC :Program Counter (continued)

20 Chapter 3 - The Processing Unit Fundamental of Computer Architecture PC :Program Counter (continued)

21 Chapter 3 - The Processing Unit Fundamental of Computer Architecture PC :Program Counter (continued)

22 Chapter 3 - The Processing Unit Fundamental of Computer Architecture PC :Program Counter (continued)

23 Chapter 3 - The Processing Unit Fundamental of Computer Architecture PC :Program Counter (continued)

24 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Branching LOC35000:LOAD R0,#0 LOAD R1,#14999 LOAD R3,#10000 LOC35003:LOAD R2,[R3] ADD R0, R2 INC R3 DEC R1 Branch_NZ LOC35003 STORE [R3],R0 [25000] = [10000]+[10002]+[10003]+….+[ 24999]

25 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Flag or Condition code Register  keep the status after perform arithmetic and logic operation Example: Flags of CPU z80

26 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Addressing modes of CPU  Immediate#value load R0,#00001  RegisterRiload R0,R1  Direct(absolute)[mem_loc] load R0,[100000]  Register indirect[Ri]load R0,[R1]  RelativeX[PC]  Index

27 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Immediate addressing  load R1,#00001

28 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Direct addressing  LOAD R1,[1200H]

29 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Register indirect  load R0,[R1]

30 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Index addressing  Use index register  Effective address = X + [Ri]  When X = offset (or displacement)  Ri = index register or Base register

31 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Index addressing Offset is given as a constant

32 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Index addressing Offset is in the index register

33 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example1 : Transfering bytes of data  Copy values in memory location 1000h-1400h to location 2000h-2400h (1024 byte)

34 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example1 : Transfering bytes of data STRT:LD R0,#1000H LD R1,#2000H LD R3,#1024 LOC_A:LD R4, [R0] STORE [R1], R4 INC R0 INC R1 DEC R3 BRANCH>0 LOC_A CALL PRINTF

35 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition  Multiply 8-bit unsigned number  C = A * B

36 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition

37 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] LOOP:ADD R1,R3 DEC R2 BRANCH>0 LOOP STORE [mem_loc_C],R1 CALL PRINTF

38 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition  Problem of the program in page 37  If B = 0 then the result is A, not 0  How to remedy the problem

39 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example2: Unsigned Multiplication by Repeated Addition STRT:LOAD R1,#0 LOAD R3, [mem_loc_A] LOAD R2, [mem_loc_B] Compare R2,#0 Branch_Z STR LOOP:ADD R1,R3 DEC R2 Branch>0 LOOP STR:STORE [mem_loc_C],R1

40 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example3: if-then-else if (mem_loc_a == 5) mem_loc_b++; else mem_loc_b = mem_loc_a + mem_loc_b;

41 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example3: if-then-else Load R1,[mem_loc_a] Load R2,[mem_loc_b] Compare r1,#5 Branch_NZ b_p_a incr2 branchstre b_p_a:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2

42 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example4: checking greater-than if (mem_loc_a > 5) mem_loc_b++; else mem_loc_b = mem_loc_a + mem_loc_b;

43 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] comparer1,#5 branch_z equ_g_5;equal 5 branch_Mequ_g_5;M= minus incr2 branchstre equ_g_5:Add r2,r1 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2

44 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Example4: checking greater-than Load R1,[mem_loc_a] Load R2,[mem_loc_b] sub r1,#5 branch>0 gt_5 Add r2,r1 branchstre gt_5:incr2 stre:Store [mem_loc_a],r1 Store [mem_loc_b],r2

45 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Basic processing unit  the structure of simple CPU  How the internal parts of CPU work  How to design the simple processor  Datapath  Control Unit

46 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Inside simple CPU with Single-bus Datapath

47 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction ADD R1,R2  MAR <= PC  ADDRESS_BUS<= MAR, read  MDR<= MEMORY[MAR]  IR<= MDR  Z<= PC + 4  PC<= Z  Y<= R1  Z<= Y + R2  R2<= Z Fetch phase Execution phase

48 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction ADD R1,R2  MAR <= PCPC out, MAR in  ADDRESS_BUS<= MAR,read read  MDR<= MEMORY[MAR] MDR inE, WMFC  IR<= MDRMDR out,IR in  Z<= PC + 4PC out, MUX_sel4, Add,Z in  PC<= ZZ out,PC in  Y<= R1Y in, R1 out  Z<= Y + R2R2 out, MUX_selY, Add, Z in  R2<= ZZ out, R2 in Active Signals

49 Chapter 3 - The Processing Unit Fundamental of Computer Architecture How to modify FETCH operation to be faster MAR <= PC ADDRESS_BUS <= MAR, Read MDR <= MEMORY[MAR], WMFC IR <= MDR Z <= PC + 4 PC <= Z MAR<= PC, Read, Z <= PC+4, MDR <= MEMORY[MAR] PC<= Z, WMFC IR<= MDR

50 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Modified FETCH operation MAR<= PC, Read, Z <= PC+4, MDR <= MEMORY[MAR] PC<= Z, WMFC IR<= MDR PCout, MARin, Read, Mux_sel4, Add, Zin Zout, PCin, Yin, WMFC MDRout, IRin Active Signals

51 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform instruction load R1,[mem_locA]  MAR <= PC, Read, Z <= PC+4, MDR <= MEMORY[MAR]  PC <= Z, WMFC  IR <= MDR  MAR <= & IR  ADDRESS_BUS<= MAR  MDR<= MEMORY[MAR]  R1<= MDR Fetch phase Execution phase

52 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Three-bus organization

53 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Perform Instruction ADD R6,R5, R4 StepAction  1PC out, R=B, MAR in, Read, incPC  2WMFC, MDR in_from_databus  3MDR out_busB, R= B, IR in  4R4 out_busB, R5 out_busA, Add, R6 in, End

54 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control Units  2 types of Control units  Hardwired  Microprogrammed

55 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control sequence for instruction ADD R1,(R3) StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4R3 out, MAR in, Read 5R1 out, Y in, WMFC 6MDR out, SelectY, Add, Z in 7Z out, R1 in, End

56 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control sequence for instruction Branch StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Offset-field-of-IR out, ADD, Z in 5Z out, PC in, End

57 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control sequence for instruction Branch<0 StepAction 1PC out, MAR in, Read, Select4, Add, Z in 2Z out, PC in, Y in, WMFC 3MDR out, IR in 4Offset-field-of-IR out, ADD, Z in, if N=0 then End 5Z out, PC in, End

58 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Hardwired Control Unit

59 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Control Unit organization

60 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Z in and END control signals Zin = T1 + (T6  ADD) + (T4  BR)+….. End = (T7  ADD) + (T5  BR) + (((T5  N)+(T4  N))  BRN)+.... Note BR = Branch instruction BRN = Branch<0 instruction N = Negative flag

61 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Generation of Z in control signal

62 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Generation of END control signal

63 Chapter 3 - The Processing Unit Fundamental of Computer Architecture Microprogrammed control unit

64 Chapter 3 - The Processing Unit Fundamental of Computer Architecture “Control words” stored in “Control Store” From Figure 7.15 page 430 of “Computer Organization”, 5 th edition, Carl Hamacher, McGraw Hill

65 Chapter 3 - The Processing Unit Fundamental of Computer Architecture จบ บทที่ 3


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