2Multiplexer-Based Transfers A dedicated multiplexer is used to select the wanted input.A simple technique using multiplexers for selection is introduced to allow multiple microoperations on a single register.From previous lecture, we saw that multiplexers and parallel load registers can be used to implement dedicated transfers from multiple sources.
3Dedicated MUX – based Transfer SELECTS0S1S2L0L1L2LOADDedicated MUX – based TransferMUX0MUX1MUX2Three n-bit 2:1 MUX, each with its own SELECT signalMUX0 : S0MUX1 : S1MUX2 : S2Each register has its own LOAD signalR0 : L0R1 : L1R2 : L2
4Dedicated MUX – based Transfer Multiplexer connected to each register input produces a very flexible structureCharacterize the simultaneous transfers possible with this structure
7MUX and Bus – based transfer for Multiple Registers A typical digital system has many registers.Paths must be provided to transfer data from one register to another.Multiplexer dedicated to each register has problems:Excessive amount of logicHigh number of interconnections
8MUX and Bus – based transfer for Multiple Registers Solution to the problem :Use a shared transfer paths for registersA shared transfer object is called a busA bus is characterized by a set of common lines, with each line driven by selection logic.Bus implementation using :MultiplexersThree – state nodes and driversIn most cases, the number of bits is the length of the receiving register
9Multiplexer BusOnly need a single n-bit 3:1 MUX and parallel load registers.MUX outputs are shared as a common path (bus)
10Multiplexer Bus SELECT signal LOAD signal Determines the contents of single source register that will appear on the MUX outputs.00 0 : R001 1 : R110 2 : R2LOAD signalDetermine the destination register / registers to be loaded with the bus data12
11Multiplexer Bus Example 1: S1, S0 = (0,0) and L0, L1, L2 = (0,0,1) thenL2 : R2 R0
12Multiplexer Bus Example 2: S1, S0 = (1,0) and L0, L1, L2 = (1,1,0) thenL0: R R2, L1 : R1 R2
13Multiplexer Bus Example 3: S1, S0 = (1,0) and L0, L1, L2 = (0,1,1) thenL1: R R2,L2 : R R2 (no change)
14Multiplexer BusA single bus driven by a MUX lowers cost, but limits the available transfersCharacterize the simultaneous transfers possible with this structure…Characterize the cost savings compared to dedicated MUX…
15Multiplexer Bus 3rd transfer : cannot be done Requires 2 simultaneous sources (R0 and R1) on a single busCannot occur in 1 clock cycleThis transfer requires at least 2 busesHowever, dedicated MUX can do this transfer
16MUX-based vs Bus-based Any combination of transfers is possibleBus-basedSimultaneous transfers from different sources in single clock cycle is impossibleReduction in hardwareLimitation in simultaneous transfers
17Three – State BusThe 3 – input MUX can be replaced by a 3 – state node (bus) and 3 – state buffersCost is further reducedSignals can travel in 2 directionsUse same bus to carry signals into and out of registers
18Three – State Bus LOAD signal ENABLE signal L0 : R0 L1 : R1 L2 : R2 E0 : R0E1 : R1E2 : R2
19Three – State BusA register with n lines that serve as both inputs and outputs.3-state buffers are enabled:The n lines are OUTPUTS.3-state buffers are disabled:The n lines are INPUTS.