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Finite Gain Effects in SC Circuits Gabor C Temes School of EECS Oregon State University Rev. 03/09/2013.

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Presentation on theme: "Finite Gain Effects in SC Circuits Gabor C Temes School of EECS Oregon State University Rev. 03/09/2013."— Presentation transcript:

1 Finite Gain Effects in SC Circuits Gabor C Temes School of EECS Oregon State University Rev. 03/09/2013

2 Non-Idealities of an Op-Amp DC offset voltage Finite dc gain Finite bandwidth Nonzero output impedance Noise 1/8

3 Model for Finite Gain 2/8

4 Model for Finite-Gain Effect ∆Q i =Y i (V i + -V i - ) ∆Q is the charge flow in one clock period. For A o  infinity, ∆Q 1 =Y 1 *V in =-∆Q 2 =-Y 2 *V o So, H(z) = -Y 1 /Y 2 when A o  infinity For finite A o : ∆Q 1 =Y 1 (V in +V o /A o ) =-∆Q 2 =-Y 2 (V o +V o /A o ) H(z) = -Y 1 /(Y 2 +Y 1 /A o +Y 2 /A o ) 3/8

5 Finite Gain Model 4/8

6 Time Domain Analysis 5/8 q 1 (n) = C 1 [v in (n)-v - (n)]=q 2 (n) q 2 (n)=-C 2 [v o (n) - v - (n) - v o (n-1)+v - (n-1)]

7 Finite D.C. Gain Effects Analysis 6/8 C 1 v in (n) = -C 2 v o (n)+v - (n)[C 1 +C 2 ]+C 2 v o [n-1] – C 2 v - (n-1) C 1 v in (n) = -C 2 [v o (n)-v o (n-1)] - [C 1 +C 2 )/A]v o (n)+(C 2 /A)v o (n-1) C 1 v in (n) =-C 2 (1+1/A)[v o (n)-v o (n-1)]+(C 1 /A)v o (n) (C 1 /A)v o (n) error is critical. It causes a phase error near dc C 2 (1+1/A)[v o (n)-v o (n-1)] error is negligible.

8 Finite D.C. Gain Effects Analysis 7/8 (C 1 /A)v o (n) error causes a phase error near dc. (C 1 /A)v o error causes phase error near dc. Φ

9 Finite Gain Model 8/8 ∞ v out v in v cmi v cmo


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