A Look Inside Intel®: The Core (Nehalem) Microarchitecture

A Look Inside Intel®: The Core (Nehalem) Microarchitecture
Beeman Strong Intel® Core™ microarchitecture (Nehalem) Architect Intel Corporation

Agenda Intel® Core™ Microarchitecture (Nehalem) Design Overview
Enhanced Processor Core Performance Features Intel® Hyper-Threading Technology New Platform New Cache Hierarchy New Platform Architecture Performance Acceleration Virtualization New Instructions Power Management Overview Minimizing Idle Power Consumption Performance when it counts

Intel® Core™ Microarchitecture (Nehalem)
Scalable Cores Same core for all segments Common software optimization Common feature set Intel® Core™ Microarchitecture (Nehalem) Servers/Workstations Energy Efficiency, Performance, Virtualization, Reliability, Capacity, Scalability 45nm Desktop Performance, Graphics, Energy Efficiency, Idle Power, Security Talk about the different attributes and why important to different segments… Mobile Battery Life, Performance, Energy Efficiency, Graphics, Security Optimized cores to meet all market segments

The First Intel® Core™ Microarchitecture (Nehalem) Processor
Memory Controller M i s c I O Core Core Q u e u e Core Core Q P I 1 Q P I 0 Shared L3 Cache QPI: Intel® QuickPath Interconnect (Intel® QPI) A Modular Design for Flexibility

Intel® Core™ Microarchitecture Recap
Wide Dynamic Execution 4-wide decode/rename/retire Advanced Digital Media Boost 128-bit wide SSE execution units Intel HD Boost New SSE4.1 Instructions Smart Memory Access Memory Disambiguation Hardware Prefetching Advanced Smart Cache Low latency, high BW shared L2 cache Nehalem builds on the great Core microarchitecture

Designed for Performance
New SSE4.2 Instructions Improved Lock Support Additional Caching Hierarchy Execution Units L1 Data Cache L2 Cache & Interrupt Servicing Memory Ordering & Execution Paging Deeper Buffers Improved Loop Streaming Out-of-Order Scheduling & Retirement Instruction Decode & Microcode Branch Prediction Instruction Fetch & L1 Cache Simultaneous Multi-Threading Better Branch Prediction Faster Virtualization

Macrofusion Introduced in Intel® Core™2 microarchitecture
TEST/CMP instruction followed by a conditional branch treated as a single instruction Decode/execute/retire as one instruction Higher performance & improved power efficiency Improves throughput/Reduces execution latency Less processing required to accomplish the same work Support all the cases in Intel Core 2 microarchitecture PLUS CMP+Jcc macrofusion added for the following branch conditions JL/JNGE JGE/JNL JLE/JNG JG/JNLE Intel® Core™ microarchitecture (Nehalem) supports macrofusion in both 32-bit and 64-bit modes Intel Core2 microarchitecture only supports macrofusion in 32-bit mode Increased macrofusion benefit on Intel® Core™ microarchitecture (Nehalem)

Intel® Core™ Microarchitecture (Nehalem) Loop Stream Detector
Loop Stream Detector identifies software loops Stream from Loop Stream Detector instead of normal path Disable unneeded blocks of logic for power savings Higher performance by removing instruction fetch limitations Higher performance: Expand the size of the loops detected (vs Core 2) Improved power efficiency: Disable even more logic (vs Core 2) Intel Core Microarchitecture (Nehalem) Loop Stream Detector Branch Prediction Fetch Decode Loop Stream Detector 28 Micro-Ops

Branch Prediction Improvements
Focus on improving branch prediction accuracy each CPU generation Higher performance & lower power through more accurate prediction Example Intel® Core™ microarchitecture (Nehalem) improvements L2 Branch Predictor Improve accuracy for applications with large code size (ex. database applications) Advanced Renamed Return Stack Buffer (RSB) Remove branch mispredicts on x86 RET instruction (function returns) in the common case Greater Performance through Branch Prediction

Execution Unit Overview
Unified Reservation Station Schedules operations to Execution units Single Scheduler for all Execution Units Can be used by all integer, all FP, etc. Execute 6 operations/cycle 3 Memory Operations 1 Load 1 Store Address 1 Store Data 3 “Computational” Operations Unified Reservation Station Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Integer ALU & Shift Integer ALU & LEA Load Store Address Store Data Integer ALU & Shift FP Multiply FP Add Branch Divide Complex Integer FP Shuffle SSE Integer ALU Integer Shuffles SSE Integer Multiply SSE Integer ALU Integer Shuffles

Increased Parallelism
1 Goal: Keep powerful execution engine fed Nehalem increases size of out of order window by 33% Must also increase other corresponding structures Structure Intel® Core™ microarchitecture (formerly Merom) Intel® Core™ microarchitecture (Nehalem) Comment Reservation Station 32 36 Dispatches operations to execution units Load Buffers 48 Tracks all load operations allocated Store Buffers 20 Tracks all store operations allocated Increased Resources for Higher Performance 1Intel® Pentium® M processor (formerly Dothan) Intel® Core™ microarchitecture (formerly Merom) Intel® Core™ microarchitecture (Nehalem)

Enhanced Memory Subsystem
Responsible for: Handling of memory operations (loads/stores) Key Intel® Core™2 Features Memory Disambiguation Hardware Prefetchers Advanced Smart Cache New Intel® Core™ Microarchitecture (Nehalem) Features New TLB Hierarchy (new, low latency 2nd level unified TLB) Fast 16-Byte unaligned accesses Faster Synchronization Primitives

Intel® Hyper-Threading Technology
Also known as Simultaneous Multi-Threading (SMT) Run 2 threads at the same time per core Take advantage of 4-wide execution engine Keep it fed with multiple threads Hide latency of a single thread Most power efficient performance feature Very low die area cost Can provide significant performance benefit depending on application Much more efficient than adding an entire core Intel® Core™ microarchitecture (Nehalem) advantages Larger caches Massive memory BW w/o SMT SMT Time (proc. cycles) Note: Each box represents a processor execution unit Simultaneous multi-threading enhances performance and energy efficiency

SMT Performance Chart Floating Point is based on SPECfp_rate_base2006* estimate Integer is based on SPECint_rate_base2006* estimate SPEC, SPECint, SPECfp, and SPECrate are trademarks of the Standard Performance Evaluation Corporation. For more information on SPEC benchmarks, see: Source: Intel. Configuration: pre-production Intel® Core™ i7 processor with 3 channel DDR3 memory. Performance tests and ratings are measured using specific computer systems and / or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit 15

Designed For Modularity
C O R E C O R E C O R E Core … L3 Cache DRAM Uncore IMC Intel® QPI Intel® QPI Power & Clock … … Intel QPI … #QPI Links # mem channels Size of cache # cores Power Manage- ment Type of Memory Integrated graphics Differentiation in the “Uncore”: Intel® QPI: Intel® QuickPath Interconnect (Intel® QPI) “Uncore” provides segment differentiation. Separate V/F domains decouples core and uncore designs. How build something modular… Core v. Uncore…. Core – adders vs. multipliers.. Uncore – things that glue all the cores together… Core and Uncore can be designed separately… Core is common across all the different solutions… Same uArch across all segments.. Good for software optimization… Common feature set… Uncore perspective… can differentiate here… # cores Size of LLC changes As we change cores, we change cache.. Type of memory… native vs. buffer Number of sockets… Integrated graphics available on some but not all… Different knobs that we can play to Q: is the common core, the same core as silverthorne/menlow… A: No – very different core. 2008 – 2009 Servers & Desktops Optimal price / performance / energy efficiency for server, desktop and mobile products

Intel® Smart Cache – 3rd Level Cache
Shared across all cores Size depends on # of cores Quad-core: Up to 8MB (16-ways) Scalability: Built to vary size with varied core counts Built to easily increase L3 size in future parts Perceived latency depends on frequency ratio between core & uncore Inclusive cache policy for best performance Address residing in L1/L2 must be present in 3rd level cache Core Core Core L1 Caches L1 Caches L1 Caches … L2 Cache L2 Cache L2 Cache L3 Cache

Why Inclusive? Inclusive cache provides benefit of an on-die snoop filter Core Valid Bits 1 bit per core per cache line If line may be in a core, set core valid bit Snoop only needed if line is in L3 and core valid bit is set Guaranteed that line is not modified if multiple bits set Scalability Addition of cores/sockets does not increase snoop traffic seen by cores Latency Minimize effective cache latency by eliminating cross-core snoops in the common case Minimize snoop response time for cross-socket cases

Intel® Core™ Microarchitecture (Nehalem-EP) Platform Architecture
Integrated Memory Controller 3 DDR3 channels per socket Massive memory bandwidth Memory Bandwidth scales with # of processors Very low memory latency Intel® QuickPath Interconnect (Intel® QPI) New point-to-point interconnect Socket to socket connections Socket to chipset connections Build scalable solutions Up to 6.4 GT/sec (12.8 GB/sec) Bidirectional (=> 25.6 GB/sec) Nehalem EP Nehalem EP Tylersburg EP IOH memory CPU Significant performance leap from new platform Intel® Core™ microarchitecture (Nehalem-EP) Intel® Next Generation Server Processor Technology (Tylersburg-EP)

Non-Uniform Memory Access (NUMA)
Nehalem EP Tylersburg EP FSB architecture All memory in one location Starting with Intel® Core™ microarchitecture (Nehalem) Memory located in multiple places Latency to memory dependent on location Local memory has highest BW, lowest latency Remote Memory still very fast Relative Memory Latency Comparison 0.00 0.20 0.40 0.60 0.80 1.00 Harpertown (FSB 1600) Nehalem (DDR3-1067) Local Remote Relative Memory Latency Ensure software is NUMA- optimized for best performance Intel® Core™ microarchitecture (Nehalem-EP) Intel® Next Generation Server Processor Technology (Tylersburg-EP)

Memory Bandwidth – Initial Intel® Core™ Microarchitecture (Nehalem) Products
3 memory channels per socket ≥ DDR at launch Massive memory BW Scalability Design IMC and core to take advantage of BW Allow performance to scale with cores Core enhancements Support more cache misses per core Aggressive hardware prefetching w/ throttling enhancements Example IMC Features Independent memory channels Aggressive Request Reordering Stream Bandwidth – Mbytes/Sec (Triad) 3.4X Source: Intel Internal measurements – August 20081 Massive memory BW provides performance and scalability 1HTN: Intel® Xeon® processor 5400 Series (Harpertown) NHM: Intel® Core™ microarchitecture (Nehalem)

Round Trip Virtualization Latency
To get best virtualized performance Have best native performance Reduce transitions to/from virtual machine Reduce latency of transitions Intel® Core™ microprocessor (Nehalem) virtualization features Reduced latency for transitions Virtual Processor ID (VPID) to reduce effective cost of transitions Extended Page Table (EPT) to reduce # of transitions Round Trip Virtualization Latency 1

EPT Solution Intel® 64 Page Tables
Base Pointer CR3 Intel® 64 Page Tables EPT Page Tables Guest Linear Address Guest Physical Address Host Physical Address Intel® 64 Page Tables Map Guest Linear Address to Guest Physical Address Can be read and written by the guest OS New EPT Page Tables under VMM Control Map Guest Physical Address to Host Physical Address Referenced by new EPT base pointer No VM Exits due to Page Faults, INVLPG or CR3 accesses

Extending Performance and Energy Efficiency - Intel® SSE4
Extending Performance and Energy Efficiency - Intel® SSE4.2 Instruction Set Architecture (ISA) Leadership in 2008 SSE4 (45nm CPUs) Faster XML parsing Faster search and pattern matching Novel parallel data matching and comparison operations Accelerated String and Text Processing STTNI SSE4.1 (Penryn Core) SSE4.2 (Nehalem Core) Improved performance for Genome Mining, Handwriting recognition. Fast Hamming distance / Population count Accelerated Searching & Pattern Recognition of Large Data Sets STTNI e.g. XML acceleration ATA (Application Targeted Accelerators) ATA Hardware based CRC instruction Accelerated Network attached storage Improved power efficiency for Software I-SCSI, RDMA, and SCTP New Communications Capabilities POPCNT e.g. Genome Mining CRC32 e.g. iSCSI Application Intel in its resolve to continue its leadership in ISA during 2008 is introducing a new set of instructions collectively called as SSE4.2. SSE4 has been defined for Intel’s 45nm products. The first version SSE4.1 was introduced in the Penryn Arch based products. A set of 7 new instructions is being introduced in Nehalem architecture in 2008 collectively called as SSE4.2. SSE4.2 is further divided into 2 distinct sub groups called STTNI and ATA. There are 4 instructions in STTNI and 2 ATA’s viz. POPCNT and CRC32. STTNI is meant for accelerated string and text processing. POPCNT is an ATA for fast pattern recognition while processing large data sets. CRC32 is another ATA that provides hardware based CRC instruction allowing for new communication capabilities What should the applications, OS and VMM vendors do?: Understand the benefits & take advantage of new instructions in 2008. Provide us feedback on instructions ISV would like to see for next generation of applications

Intel® Core™ Microarchitecture (Nehalem) Design Goals
World class performance combined with superior energy efficiency – Optimized for: Dynamically scaled performance when Single Thread Existing Apps Multi-threads Emerging Apps needed to maximize energy efficiency All Usages A single, scalable, foundation optimized across each segment and power envelope Desktop / Mobile Workstation / Server A Dynamic and Design Scalable Microarchitecture

Power Control Unit Integrated proprietary microcontroller
Vcc BCLK Core PLL Vcc Integrated proprietary microcontroller Shifts control from hardware to embedded firmware Real time sensors for temperature, current, power Flexibility enables sophisticated algorithms, tuned for current operating conditions Freq . PLL Sensors Core Vcc PCU Freq . PLL Sensors Core Vcc Freq . PLL Sensors Core Uncore , Vcc LLC Freq . PLL Sensors

Minimizing Idle Power Consumption
Operating system notifies CPU when no tasks are ready for execution Execution of MWAIT instruction MWAIT arguments hint at expected idle duration Higher numbered C-states lower power, but also longer exit latency CPU idle states referred to as “C-States” C0 Cn C1 Exit Latency (us) Idle Power (W)

C6 on Intel® Core™ Microarchitecture (Nehalem)

Core Power Time Cores 0, 1, 2, and 3 running applications.

Core Power Time Task completes. No work waiting. OS executes MWAIT(C6) instruction.

Core Power Time Execution stops. Core architectural state saved. Core clocks stopped. Cores 0, 1, and 3 continue execution undisturbed.

Core Power Time Core power gate turned off. Core voltage goes to 0. Cores 0, 1, and 3 continue execution undisturbed.

Core Power Time Task completes. No work waiting. OS executes MWAIT(C6) instruction. Core 0 enters C6. Cores 1 and 3 continue execution undisturbed.

Interrupt for Core 2 arrives. Core 2 returns to C0, execution resumes at instruction following MWAIT(C6). Cores 1 and 3 continue execution undisturbed. Core 0 Core 1 Core 2 Core 3 Core Power Time

Core Power Time Interrupt for Core 0 arrives. Power gate turns on, core clock turns on, core state restored, core resumes execution at instruction following MWAIT(C6). Cores 1, 2, and 3 continue execution undisturbed. Core independent C6 on Intel Core microarchitecture (Nehalem) extends benefits

Intel® Core™ Microarchitecture (Nehalem)-based Processor
Q P I 1 Q P I 0 Memory Controller Core Shared L3 Cache M i s c I O Q u e u e Total CPU Power Consumption Core Clocks and Logic Cores (x N) Core Clock Distribution Core Leakage Uncore Logic Significant logic outside core Integrated memory controller Large shared cache High speed interconnect Arbitration logic * Surely will be asked some why’s here… I/O Uncore Clock Distribution Uncore Leakage QPI = Intel® QuickPath Interconnect (Intel® QPI)

Intel® Core™ Microarchitecture (Nehalem) Package C-State Support
Active CPU Power All cores in C6 state: Core power to ~0 Core Clocks and Logic Cores (x N) Core Clock Distribution Core Leakage Uncore Logic Integration in combination with the flexibility of PCU, allows aggressive power reduction of components that were not well power managed in the past. I/O Uncore Clock Distribution Uncore Leakage

Active CPU Power All cores in C6 state: Core power to ~0 Package to C6 state: Uncore logic stops toggling Uncore Logic Integration in combination with the flexibility of PCU, allows aggressive power reduction of components that were not well power managed in the past. I/O Uncore Clock Distribution Uncore Leakage

Active CPU Power All cores in C6 state: Core power to ~0 Package to C6 state: Uncore logic stops toggling I/O to lower power state Integration in combination with the flexibility of PCU, allows aggressive power reduction of components that were not well power managed in the past. I/O Uncore Clock Distribution Uncore Leakage

Active CPU Power All cores in C6 state: Core power to ~0 Package to C6 state: Uncore logic stops toggling I/O to lower power state Uncore clock grids stopped Integration in combination with the flexibility of PCU, allows aggressive power reduction of components that were not well power managed in the past. I/O Uncore Clock Distribution Uncore Leakage Substantial reduction in idle CPU power

PCU automatically optimizes operating voltage
Managing Active Power Operating system changes frequency as needed to meet performance needs, minimize power Enhanced Intel SpeedStep® Technology Referred to as processor P-States PCU tunes voltage for given frequency, operating conditions, and silicon characteristics Voltage needed for a given frequency changes with number of active cores, temperature PCU automatically optimizes operating voltage

Turbo Mode: Key to Scalability Goal
Nehalem Intel® Core™ microarchitecture (Nehalem) is a scalable architecture High frequency core for performance in less constrained form factors Retain ability to use that frequency in very small form factors Retain ability to use that frequency when running lightly threaded or lower power workloads Turbo utilizes available frequency: Maximizes both single-thread and multi-thread performance in the same part Lot’s of cores in small form factors. Retain frequency capability of silicon – better upside in more power constrained form factors: more cores, lower power budget. Turbo Mode provides performance when you need it

Performance benefits with existing applications and operating systems
Turbo Mode Enabling Turbo Mode exposed as additional Enhanced Intel SpeedStep® Technology operating point Operating system treats as any other P-state, requesting Turbo Mode when it needs more performance Performance benefit comes from higher operating frequency – no need to enable or tune software Turbo Mode is transparent to system Frequency transitions handled completely in hardware PCU keeps silicon within existing operating limits Systems designed to same specs, with or without Turbo Mode Performance benefits with existing applications and operating systems

High Performance When You Need It Lower Power When You Don’t
Summary Intel® Core™ microarchitecture (Nehalem) – The 45nm Tock Designed for Power Efficiency Scalability Performance Key Innovations: Enhanced Processor Core Brand New Platform Architecture Sophisticated Power Management High Performance When You Need It Lower Power When You Don’t

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Backup Slides

Intel® Core™ Microarchitecture (Nehalem) Design Goals
World class performance combined with superior energy efficiency – Optimized for: Dynamically scaled performance when Single Thread Existing Apps Multi-threads Emerging Apps needed to maximize energy efficiency All Usages A single, scalable, foundation optimized across each segment and power envelope Desktop / Mobile Workstation / Server A Dynamic and Design Scalable Microarchitecture

Tick-Tock Development Model
Sandy Bridge Merom1 Penryn Nehalem Westmere NEW Microarchitecture 65nm NEW Process 45nm NEW Microarchitecture 45nm NEW Process 32nm NEW Microarchitecture 32nm TOCK TICK TOCK TICK TOCK Forecast 1Intel® Core™ microarchitecture (formerly Merom) 45nm next generation Intel® Core™ microarchitecture (Penryn) Intel® Core™ Microarchitecture (Nehalem) Intel® Microarchitecture (Westmere) Intel® Microarchitecture (Sandy Bridge) 53 All dates, product descriptions, availability and plans are forecasts and subject to change without notice.

Enhanced Processor Core
Front End Instruction Fetch and Pre Decode ITLB 32kB Instruction Cache Execution Engine Instruction Queue Memory Decode 4 2nd Level TLB 256kB 2nd Level Cache Rename/Allocate L3 and beyond Retirement Unit (ReOrder Buffer) 4 Reservation Station 6 Execution Units DTLB 32kB Data Cache

Front-end Responsible for feeding the compute engine
Decode instructions Branch Prediction Key Intel® Core™2 microarchitecture Features 4-wide decode Macrofusion Loop Stream Detector Instruction Fetch and Pre Decode ITLB 32kB Instruction Cache Instruction Queue Decode

Loop Stream Detector Reminder
Loops are very common in most software Take advantage of knowledge of loops in HW Decoding the same instructions over and over Making the same branch predictions over and over Loop Stream Detector identifies software loops Stream from Loop Stream Detector instead of normal path Disable unneeded blocks of logic for power savings Higher performance by removing instruction fetch limitations Intel® Core™2 Loop Stream Detector Branch Prediction Fetch Decode Loop Stream Detector 18 Instructions

Branch Prediction Reminder
Goal: Keep powerful compute engine fed Options: Stall pipeline while determining branch direction/target Predict branch direction/target and correct if wrong Minimize amount of time wasted correcting from incorrect branch predictions Performance: Through higher branch prediction accuracy Through faster correction when prediction is wrong Power efficiency: Minimize number of speculative/incorrect micro-ops that are executed Continued focus on branch prediction improvements

L2 Branch Predictor Problem: Software with a large code footprint not able to fit well in existing branch predictors Example: Database applications Solution: Use multi-level branch prediction scheme Benefits: Higher performance through improved branch prediction accuracy Greater power efficiency through less mis-speculation

Advanced Renamed Return Stack Buffer (RSB)
Instruction Reminder CALL: Entry into functions RET: Return from functions Classical Solution Return Stack Buffer (RSB) used to predict RET RSB can be corrupted by speculative path The Renamed RSB No RET mispredicts in the common case

Execution Engine Responsible for:
Scheduling operations Executing operations Powerful Intel® Core™2 microarchitecture execution engine Dynamic 4-wide Execution Intel® Advanced Digital Media Boost 128-bit wide SSE Super Shuffler (45nm next generation Intel® Core™ microarchitecture (Penryn))

Intel® Smart Cache – Core Caches
New 3-level Cache Hierarchy 1st level caches 32kB Instruction cache 32kB, 8-way Data Cache Support more L1 misses in parallel than Intel® Core™2 microarchitecture 2nd level Cache New cache introduced in Intel® Core™ microarchitecture (Nehalem) Unified (holds code and data) 256 kB per core (8-way) Performance: Very low latency 10 cycle load-to-use Scalability: As core count increases, reduce pressure on shared cache Core 32kB L1 Data Cache 32kB L1 Inst. Cache 256kB L2 Cache

New TLB Hierarchy Problem: Applications continue to grow in data size
Need to increase TLB size to keep the pace for performance Nehalem adds new low-latency unified 2nd level TLB # of Entries 1st Level Instruction TLBs Small Page (4k) 128 Large Page (2M/4M) 7 per thread 1st Level Data TLBs 64 32 New 2nd Level Unified TLB Small Page Only 512

Fast Unaligned Cache Accesses
Two flavors of 16-byte SSE loads/stores exist Aligned (MOVAPS/D, MOVDQA) -- Must be aligned on a 16-byte boundary Unaligned (MOVUPS/D, MOVDQU) -- No alignment requirement Prior to Intel® Core™ microarchitecture (Nehalem) Optimized for Aligned instructions Unaligned instructions slower, lower throughput -- Even for aligned accesses! Required multiple uops (not energy efficient) Compilers would largely avoid unaligned load 2-instruction sequence (MOVSD+MOVHPD) was faster Intel Core microarchitecture (Nehalem) optimizes Unaligned instructions Same speed/throughput as Aligned instructions on aligned accesses Optimizations for making accesses that cross 64-byte boundaries fast Lower latency/higher throughput than Core 2 Aligned instructions remain fast No reason to use aligned instructions on Intel Core microarchitecture (Nehalem)! Benefits: Compiler can now use unaligned instructions without fear Higher performance on key media algorithms More energy efficient than prior implementations

Faster Synchronization Primitives
1 Multi-threaded software becoming more prevalent Scalability of multi-thread applications can be limited by synchronization Synchronization primitives: LOCK prefix, XCHG Reduce synchronization latency for legacy software Greater thread scalability with Nehalem 1Intel® Pentium® 4 processor Intel® Core™2 Duo processor Intel® Core™ microarchitecture (Nehalem)-based processor

Intel® Core™ Microarchitecture (Nehalem) SMT Implementation Details
Policy Description Intel® Core™ Microarchitecture (Nehalem) Examples Replicated Duplicate logic per thread Register State Renamed RSB Large Page ITLB Partitioned Statically allocated between threads Load Buffer Store Buffer Reorder Buffer Small Page ITLB Competitively Shared Depends on thread’s dynamic behavior Reservation Station Caches Data TLB 2nd level TLB Unaware No SMT impact Execution units SMT efficient due to minimal replication of logic

Feeding the Execution Engine
Powerful 4-wide dynamic execution engine Need to keep providing fuel to the execution engine Intel® Core™ Microarchitecture (Nehalem) Goals Low latency to retrieve data Keep execution engine fed w/o stalling High data bandwidth Handle requests from multiple cores/threads seamlessly Scalability Design for increasing core counts Combination of great cache hierarchy and new platform Intel® Core™ microarchitecture (Nehalem) designed to feed the execution engine

Inclusive vs. Exclusive Caches – Cache Miss
L3 Cache L3 Cache Core Core 1 Core 2 Core 3 Core Core 1 Core 2 Core 3 Data request from Core 0 misses Core 0’s L1 and L2 Request sent to the L3 cache

L3 Cache L3 Cache MISS! MISS! Core Core 1 Core 2 Core 3 Core Core 1 Core 2 Core 3 Core 0 looks up the L3 Cache Data not in the L3 Cache

L3 Cache L3 Cache MISS! MISS! Core Core 1 Core 2 Core 3 Core Core 1 Core 2 Core 3 Must check other cores Guaranteed data is not on-die Greater scalability from inclusive approach

Inclusive vs. Exclusive Caches – Cache Hit
L3 Cache L3 Cache HIT! HIT! Core Core 1 Core 2 Core 3 Core Core 1 Core 2 Core 3 No need to check other cores Data could be in another core BUT Intel® CoreTM microarchitecture (Nehalem) is smart…

Inclusive vs. Exclusive Caches – Cache Hit
Maintain a set of “core valid” bits per cache line in the L3 cache Each bit represents a core If the L1/L2 of a core may contain the cache line, then core valid bit is set to “1” No snoops of cores are needed if no bits are set If more than 1 bit is set, line cannot be in Modified state in any core L3 Cache HIT! Core Core 1 Core 2 Core 3 Core valid bits limit unnecessary snoops

Inclusive vs. Exclusive Caches – Read from other core
L3 Cache L3 Cache MISS! HIT! 1 Core Core 1 Core 2 Core 3 Core Core 1 Core 2 Core 3 Must check all other cores Only need to check the core whose core valid bit is set

Local Memory Access Intel® QPI CPU0 CPU1 DRAM DRAM
CPU0 requests cache line X, not present in any CPU0 cache CPU0 requests data from its DRAM CPU0 snoops CPU1 to check if data is present Step 2: DRAM returns data CPU1 returns snoop response Local memory latency is the maximum latency of the two responses Intel® Core™ microarchitecture (Nehalem) optimized to keep key latencies close to each other Intel® QPI CPU0 CPU1 DRAM DRAM Intel® QPI = Intel® QuickPath Interconnect

Remote Memory Access CPU0 requests cache line X, not present in any CPU0 cache CPU0 requests data from CPU1 Request sent over Intel® QuickPath Interconnect (Intel® QPI) to CPU1 CPU1’s IMC makes request to its DRAM CPU1 snoops internal caches Data returned to CPU0 over Intel QPI Remote memory latency a function of having a low latency interconnect CPU0 Intel® QPI CPU1 DRAM DRAM

Hardware Prefetching (HWP)
HW Prefetching critical to hiding memory latency Structure of HWPs similar as in Intel® Core™2 microarchitecture Algorithmic improvements in Intel® Core™ microarchitecture (Nehalem) for higher performance L1 Prefetchers Based on instruction history and/or load address pattern L2 Prefetchers Prefetches loads/RFOs/code fetches based on address pattern Intel Core microarchitecture (Nehalem) changes: Efficient Prefetch mechanism Remove the need for Intel® Xeon® processors to disable HWP Increase prefetcher aggressiveness Locks on address streams quicker, adapts to change faster, issues more prefetchers more aggressively (when appropriate)

Today’s Platform Architecture

Intel® QuickPath Interconnect
Intel® Core™ microarchitecture (Nehalem) introduces new Intel® QuickPath Interconnect (Intel® QPI) High bandwidth, low latency point to point interconnect Up to 6.4 GT/sec initially 6.4 GT/sec -> 12.8 GB/sec Bi-directional link -> 25.6 GB/sec per link Future implementations at even higher speeds Highly scalable for systems with varying # of sockets Nehalem EP Nehalem EP IOH memory CPU Intel® CoreTM microarchitecture (Nehalem-EP)

Integrated Memory Controller (IMC)
Memory controller optimized per market segment Initial Intel® Core™ microarchitecture (Nehalem) products Native DDR3 IMC Up to 3 channels per socket Massive memory bandwidth Designed for low latency Support RDIMM and UDIMM RAS Features Future products Scalability Vary # of memory channels Increase memory speeds Buffered and Non-Buffered solutions Market specific needs Higher memory capacity Integrated graphics Nehalem EP Nehalem EP DDR3 DDR3 Tylersburg EP Significant performance through new IMC Intel® Core™ microarchitecture (Nehalem-EP) Intel® Next Generation Server Processor Technology (Tylersburg-EP)

Memory Latency Comparison
Low memory latency critical to high performance Design integrated memory controller for low latency Need to optimize both local and remote memory latency Intel® Core™ microarchitecture (Nehalem) delivers Huge reduction in local memory latency Even remote memory latency is fast Effective memory latency depends per application/OS Percentage of local vs. remote accesses Intel Core microarchitecture (Nehalem) has lower latency regardless of mix 1 1Next generation Quad-Core Intel® Xeon® processor (Harpertown) Intel® CoreTM microarchitecture (Nehalem)

Latency of Virtualization Transitions
Microarchitectural Huge latency reduction generation over generation Nehalem continues the trend Architectural Virtual Processor ID (VPID) added in Intel® Core™ microarchitecture (Nehalem) Removes need to flush TLBs on transitions Round Trip Virtualization Latency 1 Higher Virtualization Performance Through Lower Transition Latencies 1Intel® Core™ microarchitecture (formerly Merom) 45nm next generation Intel® Core™ microarchitecture (Penryn) Intel® Core™ microarchitecture (Nehalem)

Extended Page Tables (EPT) Motivation
A VMM needs to protect physical memory Multiple Guest OSs share the same physical memory Protections are implemented through page-table virtualization Page table virtualization accounts for a significant portion of virtualization overheads VM Exits / Entries The goal of EPT is to reduce these overheads VM1 Guest OS CR3 Guest Page Table Guest page table changes cause exits into the VMM VMM CR3 Active Page Table You might want to use the term "page-table shadowing" to describe what a VMM needs to do in software, and describe a bit more what that means -- namely that it involves a VMM making a shadow copy of the guest page tables, which requires constant maintenance by the VMM (e.g., the VMM must intercept all guest executions of CR3 and INVPLG, and often needs to handle "induced #PFs" that arise from changes that a guest OS makes to its own page tables, which must then be reflected in the shadow copy). I don't think that you need to necessarily add all of this to the foil -- you might just speak to these points -- but a bit more text to convey the nature of this work that software needs to do isn't quite coming through. Spending a bit more time here will also set you up for your final foil, where you show how EPT eliminates these overheads of VM exits on CR3 accesses, INVLPG, etc. VMM maintains the active page table, which is used by the CPU

STTNI - STring & Text New Instructions Operates on strings of bytes or words (16b)
Equal Each Instruction True for each character in Src2 if same position in Src1 is equal Src1: Test\tday Src2: tad tseT Mask: STTNI MODEL x T F t d a s e \t y Check each bit in the diagonal Source1 (XMM) Source2 (XMM / M128) IntRes1 1 Bit 0 Equal Any Instruction True for each character in Src2 if any character in Src1 matches Src1: Example\n Src2: atad tsT Mask: Ranges Instruction True if a character in Src2 is in at least one of up to 8 ranges in Src1 Src1: AZ’0’9zzz Src2: taD tseT Mask: Equal Ordered Instruction Finds the start of a substring (Src1) within another string (Src2) Src1: ABCA0XYZ Src2: S0BACBAB Mask: Equal Any : Does logical OR down each column Ranges: First Compare does GE, next does LE. Then it performs logical AND of the GE/LE pairs of results and finally OR’s those results to generate the final result. Equal ordered: Does logical AND of the results along each diagonal of the matrix. Equal Each: Check each bit in the main diagonal of the matrix. Applications benefiting from STTNI: Parsing/Tokenize GZip Virus, Spam and Intrusion Detection String Processing string.h, java.lang.string, System.string No known benchmarks Flex/Bison Compiler and state machine tools DB diffing A counted string compare RegEx Projected 3.8x kernel speedup on XML parsing & 2.7x savings on instruction cycles

STTNI Model a d t T s t d a s T e E a m x e l p \n F F T s t e a d \t
EQUAL ANY EQUAL EACH Source2 (XMM / M128) Source2 (XMM / M128) Bit 0 Bit 0 Bit 0 a d t T s OR results down each column Bit 0 t d a s T e Check each bit in the diagonal E a m x e l p \n F F T s t e a d \t y x T F x T T F x T F Source1 (XMM) Source1 (XMM) x T F x F F x T F x T F F x 1 IntRes1 1 IntRes1 RANGES EQUAL ORDERED Source2 (XMM / M128) Source2 (XMM / M128) Bit 0 Bit 0 AND the results along each diagonal t D a s T e Bit 0 S B A C AND the results along each diagonal Bit 0 Bit 0 A ‘0’ 9 Z z F T T First Compare does GE, next does LE AND GE/LE pairs of results OR those results A C B Y X Z fF F T F T fF T F x T F fF F x T F T Source1 (XMM) Source1 (XMM) Source1 (XMM) fF F T x F fT x T fT x F fT x T fT x 1 IntRes1 1 IntRes1

ATA - Application Targeted Accelerators CRC32 POPCNT
Accumulates a CRC32 value using the iSCSI polynomial POPCNT determines the number of nonzero bits in the source. Data 8/16/32/64 bit Old CRC 63 31 32 New CRC DST X Bit 1 . . . 1 1 RAX SRC  0x3 RBX =? 0 ZF One register maintains the running CRC value as a software loop iterates over data. Fixed CRC polynomial = 11EDC6F41h Replaces complex instruction sequences for CRC in Upper layer data protocols: iSCSI, RDMA, SCTP POPCNT is useful for speeding up fast matching in data mining workloads including: DNA/Genome Matching Voice Recognition ZFlag set if result is zero. All other flags (C,S,O,A,P) reset Enables enterprise class data assurance with high data rates in networked storage in any user environment.

Tools Support of New Instructions
Intel® Compiler 10.x supports the new instructions Nehalem specific compiler optimizations SSE4.2 supported via vectorization and intrinsics Inline assembly supported on both IA-32 and Intel® 64 architecture targets Necessary to include required header files in order to access intrinsics Intel® XML Software Suite High performance C++ and Java runtime libraries Version 1.0 (C++), version 1.01 (Java) available now Version 1.1 w/SSE4.2 optimizations planned for September 2008 Microsoft Visual Studio* 2008 VC++ SSE4.2 supported via intrinsics Inline assembly supported on IA-32 only VC tools masm, msdis, and debuggers recognize the new instructions Sun Studio Express* 7/08 Supports Intel® CoreTM microarchitecture (Merom), 45nm next generation Intel® Core™ microarchitecture (Penryn), Intel® CoreTM microarchitecture (Nehalem) SSE4.1, SSE4.2 through intrinsics GCC* 4.3.1 Support Intel Core microarchitecture (Merom), 45nm next generation Intel Core microarchitecture (Penryn), Intel Core microarchitecture (Nehalem) via –mtune=generic. Support SSE4.1 and SSE4.2 through vectorizer and intrinsics Intel® Integrated Performance Primitives (Intel® IPP) is an extensive library of multi-core-ready, highly optimized software functions for multimedia data processing, and communications applications. If a function is an intrinsic, the code for that function is usually inserted inline, avoiding the overhead of a function call and allowing highly efficient machine instructions to be emitted for that function. An intrinsic is often faster than the equivalent inline assembly, because the optimizer has a built-in knowledge of how many intrinsics behave, so some optimizations can be available that are not available when inline assembly is used. A header file, needs to be included that declares prototypes for the intrinsic functions. Broad Software Support for Intel® Core™ Microarchitecture (Nehalem) 85

Software Optimization Guidelines
Most optimizations for Intel® Core™ microarchitecture still hold Examples of new optimization guidelines: 16-byte unaligned loads/stores Enhanced macrofusion rules NUMA optimizations Intel® Core™ microarchitecture (Nehalem) SW Optimization Guide will be published Intel® Compiler will support settings for Intel Core microarchitecture (Nehalem) optimizations

Example Code For strlen()
int sttni_strlen(const char * src) { char eom_vals[32] = {1, 255, 0}; __asm{ mov eax, src movdqu xmm2, eom_vals xor ecx, ecx topofloop: add eax, ecx movdqu xmm1, OWORD PTR[eax] pcmpistri xmm2, xmm1, imm8 jnz topofloop endofstring: sub eax, src ret } STTNI Version string equ [esp + 4] mov ecx,string ; ecx -> string test ecx,3 ; test if string is aligned on 32 bits je short main_loop str_misaligned: ; simple byte loop until string is aligned mov al,byte ptr [ecx] add ecx,1 test al,al je short byte_3 test ecx,3 jne short str_misaligned add eax,dword ptr 0 ; 5 byte nop to align label below align 16 ; should be redundant main_loop: mov eax,dword ptr [ecx] ; read 4 bytes mov edx,7efefeffh add edx,eax xor eax,-1 xor eax,edx add ecx,4 test eax, h ; found zero byte in the loop mov eax,[ecx - 4] test al,al ; is it byte 0 je short byte_0 test ah,ah ; is it byte 1 je short byte_1 test eax,00ff0000h ; is it byte 2 je short byte_2 test eax,0ff000000h ; is it byte 3 je short byte_3 jmp short main_loop ; taken if bits are clear and bit ; 31 is set byte_3: lea eax,[ecx - 1] mov ecx,string sub eax,ecx ret byte_2: lea eax,[ecx - 2] mov ecx,string byte_1: lea eax,[ecx - 3] byte_0: lea eax,[ecx - 4] strlen endp end Imm8 is the control byte that has bit fields that controls the following attributes. Source data format : byte/word granularity, signed, unsigned etc. Aggregation operation : Encodes the mode of per-element comparison operation and aggregation of per-element comparisons into an intermediate results. Polarity : indicates any intermediate processing that needs to be performed on the intermediate result. Output selection : Depening on Index or Mask specifices the final operation to produce the output from the intermediate result. Current Code: Minimum of 11 instructions; Inner loop processes 4 bytes with 8 instructions STTNI Code: Minimum of 10 instructions; A single inner loop processes 16 bytes with only 4 instructions

CRC32 Preliminary Performance
crc32c_sse42_optimized_version(uint32 crc, unsigned char const *p, size_t len) { // Assuming len is a multiple of 0x10 asm("pusha"); asm("mov %0, %%eax" :: "m" (crc)); asm("mov %0, %%ebx" :: "m" (p)); asm("mov %0, %%ecx" :: "m" (len)); asm("1:"); // Processing four byte at a time: Unrolled four times: asm("crc32 %eax, 0x0(%ebx)"); asm("crc32 %eax, 0x4(%ebx)"); asm("crc32 %eax, 0x8(%ebx)"); asm("crc32 %eax, 0xc(%ebx)"); asm("add $0x10, %ebx")2; asm("sub $0x10, %ecx"); asm("jecxz 2f"); asm("jmp 1b"); asm("2:"); asm("mov %%eax, %0" : "=m" (crc)); asm("popa"); return crc; }} CRC32 optimized Code Preliminary tests involved Kernel code implementing CRC algorithms commonly used by iSCSI drivers. 32-bit and 64-bit versions of the Kernel under test 32-bit version processes 4 bytes of data using 1 CRC32 instruction 64-bit version processes 8 bytes of data using Input strings of sizes 48 bytes and 4KB used for the test 32 - bit 64 - bit Input Data Size = 48 bytes 6.53 X 9.85 X Input Data Size = 4 KB 9.3 X 18.63 X Preliminary Results show CRC32 instruction out-performing the fastest CRC32C software algorithm by a big margin

Idle power consumption not just mobile concern
Idle Power Matters Data center operating costs1 41M physical servers by 2010, average utilization < 10% $0.50 spent on power and cooling for every $1 spent on server hardware Regulatory requirements affect all segments ENERGY STAR* and related requirements Environmental responsibility Idle power consumption not just mobile concern IDC’s Datacenter Trends Survey, January 2007

CPU Core Power Consumption
High frequency processes are leaky Reduced via high-K metal gate process, design technologies, manufacturing optimizations Leakage Leakage and global clock distribution power are the cost of playing the high performance processor game.

High frequency designs require high performance global clock distribution High frequency processes are leaky Reduced via high-K metal gate process, design technologies, manufacturing optimizations Clock Distribution Leakage Leakage and global clock distribution power are the cost of playing the high performance processor game.

Total Core Power Consumption Local Clocks and Logic Remaining power in logic, local clocks Power efficient microarchitecture, good clock gating minimize waste High frequency designs require high performance global clock distribution High frequency processes are leaky Reduced via high-K metal gate process, design technologies, manufacturing optimizations Clock Distribution Leakage Leakage and global clock distribution power are the cost of playing the high performance processor game. Challenge – Minimize power when idle

C-State Support Before Intel® Core™ Microarchitecture (Nehalem)
Active Core Power C0: CPU active state Local Clocks and Logic Clock Distribution Leakage

Active Core Power C0: CPU active state C1, C2 states (early 1990s): Stop core pipeline Stop most core clocks Local Clocks and Logic Clock Distribution Leakage

Active Core Power C0: CPU active state C1, C2 states (early 1990s): Stop core pipeline Stop most core clocks C3 state (mid 1990s): Stop remaining core clocks Clock Distribution Leakage

Active Core Power C0: CPU active state C1, C2 states (early 1990s): Stop core pipeline Stop most core clocks C3 state (mid 1990s): Stop remaining core clocks C4, C5, C6 states (mid 2000s): Drop core voltage, reducing leakage Voltage reduction via shared VR Leakage Existing C-states significantly reduce idle power

Cores share a single voltage plane All cores must be idle before voltage reduced Independent VR’s per core prohibitive from cost and form factor perspective Deepest C-states have relatively long exit latencies System / VR handshake, ramp voltage, restore state, restart pipeline, etc. Deepest C-states available in mobile products

Intel® Core™ Microarchitecture (Nehalem) Core C-State Support
Active Core Power C0: CPU active state Local Clocks and Logic Clock Distribution Leakage

Active Core Power C0: CPU active state C1 state: Stop core pipeline Stop most core clocks Local Clocks and Logic Clock Distribution Leakage

Active Core Power C0: CPU active state C1 state: Stop core pipeline Stop most core clocks C3 state: Stop remaining core clocks Clock Distribution Leakage

Active Core Power C0: CPU active state C1 state: Stop core pipeline Stop most core clocks C3 state: Stop remaining core clocks C6 state: Processor saves architectural state Turn off power gate, eliminating leakage Leakage Core idle power goes to ~0

C6 Support on Intel® Core™2 Duo Mobile Processor (Penryn)

Cores running applications. Core 0 Core 1 Core Power Time

Task completes. No work waiting. OS executes MWAIT(C6) instruction. Core 0 Core 1 Core Power Time

Execution stops. Core architectural state saved. Core clocks stopped. Core 0 continues execution undisturbed. Core 0 Core 1 Core Power Time

Core Power Task completes. No work waiting. OS executes MWAIT(C6) instruction. Core enters C6. Time

Core Power VR voltage reduced. Power drops. Time

Interrupt for Core 1 arrives. VR voltage increased. Core 1 clocks turn on, core state restored, and core resumes execution at instruction following MWAIT(C6). Cores 0 remains idle. Core 0 Core 1 Core Power Time

Core Power Interrupt for Core 0 arrives. Core 0 returns to C0 and resumes execution at instruction following MWAIT(C6). Core 1 continues execution undisturbed. C6 significantly reduces idle power consumption Time

Reducing Platform Idle Power
Dramatic improvements in CPU idle power increase importance of platform improvements Memory power: Memory clocks stopped between requests at low utilization Memory to self refresh in package C3, C6 Link power: Intel® QuickPath Interconnect links to lower power states as CPU becomes less active PCI Express* links on chipset have similar behavior Hint to VR to reduce phases during periods of low current demand Intel® Core™ microarchitecture (Nehalem) reduces CPU and platform power

Intel® Core™ Microarchitecture (Nehalem): Integrated Power Gate
Memory System, Cache, I/O VTT VCC Integrated power switch between VR output and core voltage supply Very low on-resistance Very high off-resistance Much faster voltage ramp than external VR Enables per core C6 state Individual cores transition to ~0 power state Transparent to other cores, platform, software, and VR Close collaboration with process technology to optimize device characteristics 111

Agenda Intel® Core™ microarchitecture (Nehalem) power management overview Minimizing idle power consumption Performance when you need it

Turbo Mode Before Intel® Core™ Microarchitecture (Nehalem)
Clock Stopped Power reduction in inactive cores No Turbo Core 0 Core 1 Core 0 Core 1 Workload Lightly Threaded Frequency (F) Frequency (F) OEM adheres to thermal design guidelines Works with Enhanced Intel Speedstep to increase energy efficiency Capability extends further in Sandy Bridge 113 113 113 113

Turbo Mode Before Intel® Core™ Microarchitecture (Nehalem)
Clock Stopped Power reduction in inactive cores Turbo Mode In response to workload adds additional performance bins within headroom No Turbo Core 0 Core 1 Core 0 Workload Lightly Threaded Frequency (F) Frequency (F) OEM adheres to thermal design guidelines Works with Enhanced Intel Speedstep to increase energy efficiency Capability extends further in Sandy Bridge 114 114 114 114

Intel® Core™ Microarchitecture (Nehalem) Turbo Mode
Power Gating Zero power for inactive cores No Turbo Core 0 Core 1 Core 2 Core 3 Core 0 Core 1 Core 2 Core 3 Workload Lightly Threaded or < TDP Frequency (F) Frequency (F) OEM adheres to thermal design guidelines Works with Enhanced Intel Speedstep to increase energy efficiency Capability extends further in Sandy Bridge 115 115 115 115

Zero power for inactive cores
Intel® Core™ Microarchitecture (Nehalem) Turbo Mode Power Gating Zero power for inactive cores Turbo Mode In response to workload adds additional performance bins within headroom No Turbo Core 0 Core 1 Core 2 Core 3 Core 0 Core 1 Workload Lightly Threaded or < TDP Frequency (F) Frequency (F) OEM adheres to thermal design guidelines Works with Enhanced Intel Speedstep to increase energy efficiency Capability extends further in Sandy Bridge 116 116 116 116

Zero power for inactive cores
Intel® Core™ Microarchitecture (Nehalem) Turbo Mode Power Gating Zero power for inactive cores Turbo Mode In response to workload adds additional performance bins within headroom No Turbo Core 0 Core 1 Core 2 Core 3 Core 0 Core 1 Workload Lightly Threaded or < TDP Frequency (F) Frequency (F) OEM adheres to thermal design guidelines Works with Enhanced Intel Speedstep to increase energy efficiency Capability extends further in Sandy Bridge 117 117 117 117

Active cores running workloads < TDP
Intel® Core™ Microarchitecture (Nehalem) Turbo Mode Active cores running workloads < TDP No Turbo Core 0 Core 1 Core 2 Core 3 Core 0 Core 1 Core 2 Core 3 Workload Lightly Threaded or < TDP Core 1 Core 3 Frequency (F) Core 0 Core 2 Frequency (F) OEM adheres to thermal design guidelines Works with Enhanced Intel Speedstep to increase energy efficiency Capability extends further in Sandy Bridge 118 118 118 118

Active cores running workloads < TDP
Intel® Core™ Microarchitecture (Nehalem) Turbo Mode Active cores running workloads < TDP Turbo Mode In response to workload adds additional performance bins within headroom No Turbo Core 0 Core 1 Core 2 Core 3 Core 2 Workload Lightly Threaded or < TDP Frequency (F) Frequency (F) Core 0 Core 1 Core 3 OEM adheres to thermal design guidelines Works with Enhanced Intel Speedstep to increase energy efficiency Capability extends further in Sandy Bridge 119 119 119 119

Dynamically Delivering Optimal Performance and Energy Efficiency
Intel® Core™ Microarchitecture (Nehalem) Turbo Mode Power Gating Zero power for inactive cores Turbo Mode In response to workload adds additional performance bins within headroom No Turbo Core 0 Core 1 Core 2 Core 3 Core 2 Workload Lightly Threaded or < TDP Frequency (F) Core 0 Frequency (F) Core 1 Core 3 Dynamically Delivering Optimal Performance and Energy Efficiency 120 120 120 120

Additional Sources of Information on This Topic:
Other Sessions / Chalk Talks / Labs: TCHS001: Next Generation Intel® Core™ Microarchitecture (Nehalem) Family of Processors: Screaming Performance, Efficient Power (8/19, 3:00 – 3:50) DPTS001: High End Desktop Platform Design Overview for the Next Generation Intel® Microarchitecture (Nehalem) Processor (8/20, 2:40 – 3:30) NGMS001: Next Generation Intel® Microarchitecture (Nehalem) Family: Architectural Insights and Power Management (8/19, 4:00 – 5:50) NGMC001: Chalk Talk: Next Generation Intel® Microarchitecture (Nehalem) Family (8/19, 5:50 – 6:30) NGMS002: Tuning Your Software for the Next Generation Intel® Microarchitecture (Nehalem) Family (8/20, 11:10 – 12:00) PWRS003: Power Managing the Virtual Data Center with Windows Server* 2008 / Hyper-V and Next Generation Processor-based Intel® Servers Featuring Intel® Dynamic Power Technology (8/19, 3:00 – 3:50) PWRS005: Platform Power Management Options for Intel® Next Generation Server Processor Technology (Tylersburg-EP) (8/21, 1:40 – 2:30) SVRS002: Overview of the Intel® QuickPath Interconnect (8/21, 11:10 – 12:00)

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A Look Inside Intel®: The Core (Nehalem) Microarchitecture

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A Look Inside Intel®: The Core (Nehalem) Microarchitecture

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