1. 1 Scaleable Architecture for Real-Time Applications, SARA Lennart Lindh, Tommy Klevin and Johan Furunäs, Department of Computer Engineering (IDT), Mälardalens Real-Time Center (MRTC) Mälardalens University, Sweden (http://www.mrtc.mdh.se/cal/)

2. 2 Application Control System

3. 3 “Robot” Problems Today Performance (>3 Processors today) Functionality in the base system (RTOS) –Communication protocol Static coupled multi-processor system We have added: –Predictability (robotics have some hard deadlines) –Observability and controllability –Small Overhead (simplification) –Fault Tolerance –Component oriented design

4. 4 Mixed HW/SW implementation Hardware Software Hardware The research question is: will it be possible to meet the SARA’s objectives if software functions and functions implements in hardware?

5. 5 Yesterday, Today and Tomorrow

6. 6 Presentation of SARA, Scaleable Architecture for Real-Time Applications The SARA Approach Logical and physical architecture Hardware and Software Some benchmark results Conclusions

7. 7 SARA Approach (main objectives) Performance –Scalability Predictability (HW/SW) Simple Observability and controllability Component oriented design –“adapter” for different standards Fault Tolerance

8. 8 Logical architecture

9. 9 Priority inheritance of the mail priorities Event A, Low priority Event B, High priority Tasks (Servers)  IPC-SEND // For asynchrony messages  IPC-SENDWAIT// For synchrony messages  IPC-BROADCAST// For broadcast messages  IPC-DISTRIBUTE//For multicast messages

10. 10 Hard tasks (Servers) Software part for the IPC bus Hardware part for the IPC bus IPC Bus Hardware Task Hardware design Formal methods Deadline controls 8-16 bits applications

11. 11 Use of old software Software part for the IPC bus Hardware part for the IPC bus IPC Bus Old RTOS Old Application

12. 12 Physical architecture PPC750, L1,L2 System on a Chip Standard systems Write/Read

13. 13 Hardware and Software

14. 14 Communication between RTU and CPU RT-clock IRQ Handler RTU HW- Interrupt Scheduler CPU RTU-gränssnitt Avbrottsrutin för taskswitch Semaphore CPU RTU-I/O Task switch handler

15. 15 IRQ-Handler Hardware and Software mult_resp2(utan Cach) –task1470.7  s –task2634.4  s mult_resp2 (with Cach) – task1452.9  s –task2602.9  s mult_resp2 –task1 156,2  s –task2 326,5  s

16. 16 Kernel Overhead in Hardware

17. 17 Conclusion The IPC is easy to use When a software function implements in hardware the response time and time gap between best and worst case execution time decrease, ex in RTU clock tick is 1us, in a software system 1ms. (RTU need 5 MHz) Demonstration of the SARA on SNART. Are you interesting in corporation?