1. EE 201A/EE298 Modeling and Optimization for VLSI Layout
Instructor: Lei He

2. Outline Course logistics Overview What are covered in the course
What are interesting trends for physical design
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

3. Instructor Info
Phone:
Office: Engineering IV
Office hours: Tu/Th 2-3pm or by appointment
The best way to reach me:
with EE201 in subject line
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

4. About this Course
One of selective course for EE’s ECS Major Field Students
Question in M.S. comprehensive exam / PhD prelims
Offered every other spring
Will be under another course number (EE205B)
Related courses
Mani’s EE202A Embedded Computing Systems (Fall)
Ingrid’s EE201A on Advanced VLSI (Spring)
Bill M-S’s EE204A on Compilers (Winter)
My EE205A Fundamental to CAD (Winter)
Mani’s EE206A Wireless Systems (Spring)
My EE205B (every other Spring)
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

5. Course Prerequisites Official prerequisite
EE116B VLSI System Design
But mainly self-contained
Knowledge to help you appreciate more
CS180 Introduction to algorithms
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

6. EE205A and EE205B EE205A Fundamental to CAD of embedded systems
System level performance/power/thermal modeling and optimization
Synthesis – scheduling and allocation, logic optimization and technology mapping
FPGA circuits and architectures and placement and routing for FPGA
EE205B Modeling and Optimization for VLSI layout
Advanced algorithms for physical design
Fundamentals of combinatorial algorithm
Detailed performance, signal integrity, power and thermal models
Incorporating physical design into system design
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

7. VLSI Design Cycle System Specification Functional Design
Logic Design
Circuit Design
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))

8. VLSI Design Cycle (cont.)
Physical Design
Fabrication
Packaging

9. Simplified Physical Design Cycle
Partition
Front-end
physical design
Floorplanning
Placement
Routing
Back-end
physical design
Extraction and Verification

10. Course Outline and Schedule
Front-end physical design (4.5 weeks)
Partitioning, floorplanning and placement
Power and thermal modeling
Algorithms: divided and conquer, simulated annealing, genetic algorithm
Project proposal due by end of fifth week
Back-end physical design (4.5 weeks)
Interconnect extraction and modeling
Interconnect synthesis
Noise modeling and avoidance
Clock and power supply design **
Algorithms: dynamic programming, linear programming
Project report due the last day of the quarter

11. Related VLSI CAD Conferences
ACM IEEE Design Automation Conference (DAC)
(San Diego, Young student program)
International Conference on Computer Aided Design(ICCAD)
Design, Automation and Test in Europe (DATE)
Asia and South Pacific Design Automation Conference (ASP-DAC)
International symposium on physical design (ISPD)
International symposium on low power electronics and design
International symposium on field programmable gate array
IEEE International Symposium on Circuits and Systems (ISCAS)

12. Related VLSI CAD Journals
IEEE Transactions on CAD of Circuits and systems (TCAD)
ACM Trans. on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Circuits and Systems (TCAS)
IEEE Trans. on VLSI Systems (TVLSI)
IEEE Trans. on Computer
Integration
Algorithmica
SIAM journal of Discrete and Applied Mathematics

13. Money Talk for VLSI CAD Synposys, Cadence, Magma, Mentor Graphics, …
Over hundreds companies have booths at DAC
Two of them are among the ten biggest software companies in the world
But they are smaller than the biggest spin-off of EDA
EDA is regarded as A-graded bonds for Venture Capitalists
One of few IT segments still recruits heavily and offers salary higher than Intel/IBM
EDA system is regarded as one of the most complicated software systems mankind ever built

14. References for this Course
Selected papers from TCAD, TODAES, and major CAD conferences such as DAC, ICCAD and ISPD
Naveed A. Sherwani, "Algorithms for VLSI Physical Design Automation", 3rd Edition, 1998.
H. Cormen, et al “Introduction to Algorithms” MIT Electrical Engineering and Computer Science Series 1990.
H. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison Wesley
Cong et al., Performance Optimization of VLSI Interconnect Layout, Integration, the VLSI Journal 21 (1996)
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

15. Grading Policy Homework 15% Midterm (7th week) 20%
Course presentation 15%
Term project 50%
A  score > 85 and programming project
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

16. Course Presentation (15%)
2~3 student a team
Survey an area (topics and resources specified by me on a continual basis)
Prepare slides and do a minute presentation in the class
slides prepared jointly
either all students share the presentation or I will select the speaker randomly at the presentation time
Prepare a web site that should contain a report based on your survey, a bibliography, and links to resources and of course your slides

17. Term Project (50%) One of the following two:
One-person survey and critic of selected topic (at most 35%)
Individual programming project for a team of 2 to 3 persons
Coupled system design and physical design
Floorplanning with thermal constraints
3D modeling and physical design
Or any topic agreed by instructor
Up to 30 minute presentation during the finals week, like a conference talk
Up to 12 page report in the style of a technical conference paper
ACM style

18. Who should take this course
It is another course
Discuss wide scope of knowledge
But research (presentation + project) on your own focus
For students who are motivated to
Learn SI, power/thermal for advanced designs
Learn algorithm basics without taking CS280
Understand CAD better
Become a CAD professional
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

19. Complexities of Physical Design
More than 10 million transistor
Performance driven designs
Time-to-Market
Design cycle
High performance, high cost
…...

20. Moore’s Law and NTRS Moore’s Law
The min. transistor feature size decreases by 0.7X every three years (Electronics Magazine, Vol. 38, April 1965)
True in the past 30 years, and expected to hold for another years
National Technology Roadmap for Semiconductors (NTRS’97)

21. Productivity Gap Chip Capacity and Designer Productivity
10,000,000
100,000,000
1,000,000
10,000,000
58%/Yr. Complexity
growth rate
100,000
1,000,000
Logic Transistors/Chip (K)
Transistor/Staff-Month
10,000
100,000
1,000
10,000
21%/Yr.
Productivity growth rate
100 x x
1,000 x x x x x 10 x
100 1 10
1998
2003
Chip Capacity and Designer Productivity
Source: NTRS’97

22. Design Challenges in Nanometer Technologies
Interconnect-limited designs
Interconnect performance limitation
Interconnect modeling complexity
Interconnect reliability
Impact of new interconnect materials
Small feature size
Process variations
Leakage (~50% of total power)
High degree of on-chip integration
Complexity and productivity
Limitation of current design abstraction and hierarchy
System on a chip and system in package or 3D technology
Power/thermal barrier

23. Design Styles Complexity of VLSI circuits Full custom Performance Size
Cost
Market time
Standard Cell
Gate Array
FPGA
Different design styles
Cost ,Flexibility,Performance

24. Full Custom Design Style
Pad
Metal
Via
Metal 2
I/O
Data Path
ROM/RAM
PLA
A/D Converter
Random logic

25. Standard Cell Design Style
VDD
Metal 1
Cell
Metal 2
Feedthrough
GND D C B A
Cell A
Cell C
Cell B
Cell D
Feedthrough cell

26. Gate Array Design Style (or Structured ASIC)B C
VDD
Metal1
Metal2

27. Field-Programmable Gate-Arrays (FPGAs)
Programmable logic
Programmable interconnects
Programmable inputs/outputs

28. FPGA Design Style

29. Comparisons of Design Styles
* uneven height cells are also used

30. Comparisons of Design Styles
Area
Performance
Fabrication layers
style
full-custom
standard cell
gate array
FPGA
compact
high
to moderate
moderate
large
low
ALL
routing layers
none

31. Printed Circuit Board PCB Wafer Scale Integration WSI or 3D
Packaging Styles
Printed Circuit Board PCB
Multi-Chip Module MCM
Wafer Scale Integration WSI or 3D
Packaging
Area
Performance, cost
The increasing complexity and density of the semiconductor devices are driving the development of more advanced VLSI packaging and interconnection approaches.

32. Printed Circuit Board Model
Large number of layers (150a pitch)
Larger area
Low performance
Low cost
Package
Plated through holes IC
( a )
( b )

33. MCM Model Up to 36 layers ( 75a pitch) Moderate to small area
Moderate to high performance
High cost
Heat dissipation problems IC
( a )
( b )

34. Wafer Scale Integration
Small number of layers (VLSI technology- 6a pitch)
Smallest area
Significant yield problems
Very high performance
Significant heat dissipation problems

35. Comparisons of Packaging Styles
Merit = propagation speed (inches/psec.) * interconnection density (inches/sq. in).
Interconnect resistance was not considered

36. Increasingly on the Same Chip or in the Same Package (SoC and SiP)
SC3001 DIRAC chip (Sirius Communications)

37. History of VLSI Layout Tools
One of the new trends: SoC and SiP for 3D technology

38. Summary
Physical design is the most complicated step in the VLSI design cycle
Physical design is further divided into clustering, partitioning, floorplanning, placement, global and detailed routing. Extraction and verification is an important aspect.
There are four major design styles -- full custom, standard cell, gate array (structured ASIC), and FPGAs.
There are three alternatives for packaging of chips -- PCB, MCM and WSI. But increasingly, we design for SoC and SiP and will use 3D technology
Automation reduces cost, increases chip density, reduces time-to-market, and improves performance.
CAD tools currently lag behind fabrication technology, which is hindering the progress of IC technology

39. Homework (due April 14th)
Read ITRS roadmap executive summary and write one page summary and critic on one aspect related to your research or field
Search literature or web related to SoC, SiP and 3D technology, summarize five papers on a coherent topic (e.g., technology, design, or CAD) and speculate potential need of CAD research
Following style of conference paper
With course project proposal in mind
Submit homework in PDF via
Check out course website for notes of future lectures