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EE 201A/EE298 Modeling and Optimization for VLSI Layout Instructor: Lei He

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Presentation on theme: "EE 201A/EE298 Modeling and Optimization for VLSI Layout Instructor: Lei He"— Presentation transcript:

1 EE 201A/EE298 Modeling and Optimization for VLSI Layout Instructor: Lei He

2 Outline n Course logistics n Overview  What are covered in the course  What are interesting trends for physical design

3 Instructor Info n n Phone: n Office: Engineering IV n Office hours: Tu/Th 2-3pm or by appointment n The best way to reach me:  with EE201 in subject line

4 About this Course n One of selective course for EE’s ECS Major Field Students  Question in M.S. comprehensive exam / PhD prelims  Offered every other spring  Will be under another course number (EE205B) n Related courses  Mani’s EE202A Embedded Computing Systems (Fall)  Ingrid’s EE201A on Advanced VLSI (Spring)  Bill M-S’s EE204A on Compilers (Winter)  My EE205A Fundamental to CAD (Winter)  Mani’s EE206A Wireless Systems (Spring)  My EE205B (every other Spring)

5 Course Prerequisites n Official prerequisite  EE116B VLSI System Design  But mainly self-contained n Knowledge to help you appreciate more  CS180Introduction to algorithms

6 EE205A and EE205B n EE205A Fundamental to CAD of embedded systems  System level performance/power/thermal modeling and optimization  Synthesis – scheduling and allocation, logic optimization and technology mapping  FPGA circuits and architectures and placement and routing for FPGA n EE205B Modeling and Optimization for VLSI layout  Advanced algorithms for physical design  Fundamentals of combinatorial algorithm  Detailed performance, signal integrity, power and thermal models  Incorporating physical design into system design

7 System Specification Functional Design Logic Design Circuit Design X=(AB*CD)+(A+D)+(A(B+C)) Y=(A(B+C))+AC+D+A(BC+D)) VLSI Design Cycle

8 Physical Design Fabrication Packaging VLSI Design Cycle (cont.)

9 Partition Floorplanning Placement Simplified Physical Design Cycle Routing Extraction and Verification Front-end physical design Back-end

10 Course Outline and Schedule n Front-end physical design (4.5 weeks)  Partitioning, floorplanning and placement  Power and thermal modeling  Algorithms: divided and conquer, simulated annealing, genetic algorithm  Project proposal due by end of fifth week n Back-end physical design (4.5 weeks)  Interconnect extraction and modeling  Interconnect synthesis  Noise modeling and avoidance  Clock and power supply design **  Algorithms: dynamic programming, linear programming  Project report due the last day of the quarter

11 ACM IEEE Design Automation Conference (DAC) (San Diego, Young student program) International Conference on Computer Aided Design(ICCAD) Design, Automation and Test in Europe (DATE) Asia and South Pacific Design Automation Conference (ASP- DAC) International symposium on physical design (ISPD) International symposium on low power electronics and design International symposium on field programmable gate array IEEE International Symposium on Circuits and Systems (ISCAS) Related VLSI CAD Conferences

12 IEEE Transactions on CAD of Circuits and systems (TCAD) ACM Trans. on Design Automation of Electronic Systems (TODAES) IEEE Transactions on Circuits and Systems (TCAS) IEEE Trans. on VLSI Systems (TVLSI) IEEE Trans. on Computer Integration Algorithmica SIAM journal of Discrete and Applied Mathematics Related VLSI CAD Journals

13 Synposys, Cadence, Magma, Mentor Graphics, … Over hundreds companies have booths at DAC Two of them are among the ten biggest software companies in the world But they are smaller than the biggest spin-off of EDA EDA is regarded as A-graded bonds for Venture Capitalists One of few IT segments still recruits heavily and offers salary higher than Intel/IBM EDA system is regarded as one of the most complicated software systems mankind ever built Money Talk for VLSI CAD

14 References for this Course Selected papers from TCAD, TODAES, and major CAD conferences such as DAC, ICCAD and ISPD Selected papers from TCAD, TODAES, and major CAD conferences such as DAC, ICCAD and ISPD Naveed A. Sherwani, "Algorithms for VLSI Physical Design Automation", 3rd Edition, Naveed A. Sherwani, "Algorithms for VLSI Physical Design Automation", 3rd Edition, H. Cormen, et al “Introduction to Algorithms” MIT Electrical Engineering and Computer Science Series H. Cormen, et al “Introduction to Algorithms” MIT Electrical Engineering and Computer Science Series H. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison Wesley H. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison Wesley Cong et al., Performance Optimization of VLSI Interconnect Layout, Integration, the VLSI Journal 21 (1996) Cong et al., Performance Optimization of VLSI Interconnect Layout, Integration, the VLSI Journal 21 (1996)

15 Grading Policy n Homework15% n Midterm (7 th week)20% n Course presentation15% n Term project50% n A  score > 85 and programming project

16 Course Presentation (15%) n 2~3 student a team n Survey an area (topics and resources specified by me on a continual basis) n Prepare slides and do a minute presentation in the class  slides prepared jointly  either all students share the presentation or I will select the speaker randomly at the presentation time n Prepare a web site that should contain a report based on your survey, a bibliography, and links to resources and of course your slides

17 Term Project (50%) One of the following two: One of the following two:  One-person survey and critic of selected topic (at most 35%)  Individual programming project for a team of 2 to 3 persons  Coupled system design and physical design  Floorplanning with thermal constraints  3D modeling and physical design  Or any topic agreed by instructor n Up to 30 minute presentation during the finals week, like a conference talk n Up to 12 page report in the style of a technical conference paper  ACM style

18 Who should take this course n It is another course  Discuss wide scope of knowledge  But research (presentation + project) on your own focus n For students who are motivated to  Learn SI, power/thermal for advanced designs  Learn algorithm basics without taking CS280  Understand CAD better  Become a CAD professional

19   More than 10 million transistor   Performance driven designs   Time-to-Market Design cycle High performance, high cost …... Complexities of Physical Design

20 Moore’s Law and NTRS n Moore’s Law  The min. transistor feature size decreases by 0.7X every three years (Electronics Magazine, Vol. 38, April 1965)  True in the past 30 years, and expected to hold for another years n National Technology Roadmap for Semiconductors (NTRS’97)

21 Productivity Gap x x x x x x x 21%/Yr. Productivity growth rate x 58%/Yr. Complexity growth rate ,000 10, ,000 1,000,000 10,000, ,000 10, ,000 1,000,000 10,000, ,000,000 Logic Transistors/Chip (K) Transistor/Staff-Month Chip Capacity and Designer Productivity 2003 Source: NTRS’97

22 Design Challenges in Nanometer Technologies n Interconnect-limited designs  Interconnect performance limitation  Interconnect modeling complexity  Interconnect reliability  Impact of new interconnect materials n Small feature size  Process variations  Leakage (~50% of total power) n High degree of on-chip integration  Complexity and productivity  Limitation of current design abstraction and hierarchy  System on a chip and system in package or 3D technology  Power/thermal barrier

23 Complexity of VLSI circuits Full custom PerformanceSizeCostMarket time Standard CellGate ArrayFPGA Different design styles Cost,Flexibility,Performance Design Styles

24 Full Custom Design Style PadMetalViaMetal 2 I/O Data Path ROM/RAM PLA A/D Converter Random logic

25 Standard Cell Design Style VDD Metal 1 Cell Metal 2 Feedthrough GND DCCB ACC DCDB CCCB Cell A Cell C Cell B Cell D Feedthrough cell

26 Gate Array Design Style (or Structured ASIC) A B C A B C VDDMetal1Metal2

27   Programmable logic   Programmable interconnects   Programmable inputs/outputs Field-Programmable Gate-Arrays (FPGAs)

28 FPGA Design Style

29 Comparisons of Design Styles * uneven height cells are also used style

30 Area Performance Fabrication layers style full-customstandard cellgate arrayFPGA compact high compact to moderate moderatelarge high to moderate moderatelow ALL routing layers none Comparisons of Design Styles

31 Printed Circuit Board PCB Multi-Chip Module MCM Wafer Scale Integration WSI or 3D Packaging Area Performance, cost The increasing complexity and density of the semiconductor devices are driving the development of more advanced VLSI packaging and interconnection approaches. Packaging Styles

32 Printed Circuit Board Model   Large number of layers (150a pitch)   Larger area   Low performance   Low cost Package Plated through holes IC( a ) ( b )

33 MCM Model   Up to 36 layers ( 75a pitch)   Moderate to small area   Moderate to high performance   High cost   Heat dissipation problems IC ( a ) ( b )

34 Wafer Scale Integration   Small number of layers (VLSI technology- 6a pitch)   Smallest area   Significant yield problems   Very high performance   Significant heat dissipation problems

35 Comparisons of Packaging Styles   Merit = propagation speed (inches/psec.) * interconnection density (inches/sq. in).   Interconnect resistance was not considered

36 Increasingly on the Same Chip or in the Same Package (SoC and SiP) n SC3001 DIRAC chip (Sirius Communications)

37 History of VLSI Layout Tools One of the new trends: SoC and SiP for 3D technology

38 Summary  Physical design is the most complicated step in the VLSI design cycle  Physical design is further divided into clustering, partitioning, floorplanning, placement, global and detailed routing. Extraction and verification is an important aspect.  There are four major design styles -- full custom, standard cell, gate array (structured ASIC), and FPGAs.  There are three alternatives for packaging of chips -- PCB, MCM and WSI. But increasingly, we design for SoC and SiP and will use 3D technology  Automation reduces cost, increases chip density, reduces time-to-market, and improves performance.  CAD tools currently lag behind fabrication technology, which is hindering the progress of IC technology

39 Homework (due April 14 th )  Read ITRS roadmap executive summary and write one page summary and critic on one aspect related to your research or field   Search literature or web related to SoC, SiP and 3D technology, summarize five papers on a coherent topic (e.g., technology, design, or CAD) and speculate potential need of CAD research  Following style of conference paper  With course project proposal in mind  Submit homework in PDF via  Check out course website for notes of future lectures 

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