3 IntroductionA Structured ASIC falls between an FPGA and a Standard Cell-based ASICStructured ASIC’s are used mainly for mid-volume level designsThe design task for structured ASIC’s is to map the circuit into a fixed arrangement of known cells
4 Properties Low NRE cost High performance Low power consumption Implementation engineering effortMask tooling chargesHigh performanceLow power consumptionLess ComplexFewer layers to fabricateSmall marketing timePre-made cell blocks available for placing
5 Architecture Two Main Levels Structured Elements Combinational and sequential function blocksCan be a logical or storage elementArray of Structured ElementsUniform or non-uniform array stylesA fixed arrangement of structured elements
6 Main Implementation Steps RTL DesignRegister transfer level designLogical synthesisMaps RTL into structured elementsDesign for Test insertionImproves testability and fault coveragePlacementMaps each structured element onto array elementsPlaces each element into a fixed arrangement
7 Main Implementation Steps Physical synthesisImproves the timing of the layoutOptimizes the placement of each elementClock synthesisDistributes the clock networkMinimizes the clock skew and delayRoutingInserts the wiring between the elements
8 Implementation Issues Logical synthesis, placement and routing all depend on the target structure element architecture and hence add more complexity to the design process.The completeness of the target structured ASIC library also affects what specifically can be implemented from the design.
9 Structured ASIC’s Combine the Best of Both Worlds FPGAStandard Cell ASICVs.Easy to DesignShort Development TimeLow NRE CostsDesign Size LimitedDesign Complexity LimitedPerformance LimitedHigh Power ConsumptionHigh Per-Unit CostDifficult to DesignLong Development TimeHigh NRE CostsSupport Large DesignsSupport Complex DesignsHigh PerformanceLow Power ConsumptionLow Per-Unit Cost (at high volume)Structured ASIC’s Combine the Best of Both Worlds
10 Structured ASIC Architectures Fine-Grained Structured elements contain unconnected discrete componentsCould include transistors, resistors, and others
11 Structured ASIC Architectures Medium-Grained Structured elements contain generic logicCould include gates, MUX’s, LUT’s or flip-flops
12 Structured ASIC Architectures Hierarchical Use mini structured elements that contain only gates, MUX’s, and LUT’sIt does not contain storage elements like flip-flopsThis mini element is then combined with registers or flip-flops
13 Architecture Comparison Fine-grained requires many connections in and out of a structured elementHigher granularities reduce connections to the structured element but decreases the functionality it can supportClearly, each individual design will benefit differently at varying granularities
14 Structured ASIC Advantages Largely PrefabricatedComponents are “almost” connected in a variety of predefined configurationsOnly a few metal layers are needed for fabricationDrastically reduces turnaround timePre-Routed LayerRouting Layer
15 Structured ASIC Advantages Easier and faster to design than standard cell ASIC’sMultiple global and local clocks are prefabricatedNo skew problems that need to be addressedSignal integrity and timing issues are inherently addressed
16 Structured ASIC Advantages Capacity, performance, and power consumption closer to that of a standard cell ASICFaster design time, reduced NRE costs, and quicker turnaroundTherefore, the per-unit cost is reasonable for several hundreds to 100k unit production runs
17 Structured ASIC Disadvantages Lack of adequate design toolsExpensiveAltered from traditional ASIC toolsThese new architectures have not yet been subject to formal evaluation and comparative analysisTradeoffs between 3-, 4-, and 5-input LUT’sTradeoffs between sizes of distributed RAM
18 Technology Comparison Generally speaking100:33:1 ratio between the number of gates in a given area for standard cell ASIC’s, structured ASIC’s, and FPGA’s, respectively100:75:15 ratio for performance (based on clock frequency)1:3:12 ratio for power
19 Design ToolsMany companies are using existing standard cell-based CAD toolsThey add product specific placement toolsTo maximize benefits, we need CAD tools designed specifically for structured ASIC’sNeed updated algorithms to exploit the modularity of structured ASIC’sClock aware designNeed architectural evaluation and analysis tools
20 Case Study: NEC ISSP Problem Formulation PrefabricatedStandard Cells, Flip-Flops, DSP, Memory and other IP (Intellectual Properties)Interconnects for modules, DFT circuit, and clocksPhysical Design (Placement) ProblemsModules are already embeddedMapping problem
21 After Logical Synthesis Different clock signals for different groups of modules (FFs)Multiple clock signals in one chipMust perform clock-aware placement
22 Embedded Clocks2 main clocksAccessible from anywhere
23 Embedded Clocks 8 local clocks Chip divided into 4 regions 4 local clocks can be assigned to each regionRegion divided into 4 sub regionsEach subregion assigned 2 local clocks
24 More Clock Signals Needed? Use a custom layer to implement an additional clock signalCustom layer is limited, so it many not be feasibleTry to avoid this as much as possible
25 Assigning Clock Signal Main/local clock assignmentWhich clock should be the main clock?Which clock should be the local clock?Region clock assignmentWhich local clock should be assigned to each region?Do we need a custom clock?We generally do not want it3 methods to solve this
26 Number Based Heuristics Method 1 Assign 2 most used clocks as main clocksOther clocks are local clocksAssign local clocks to subregions based on I/O positionsPerform placementProblemsMay not be possibleWhat about delay optimization?
27 Placement Based Clock Optimization Method 2 Perform placement without clock constrainsBased on interconnect delaysClock assignment as result of step 1Which clock should be the main clock?Which local clock should be assigned to each region?Move violating FFs to other regionsMap FFs to embedded positions
28 Placement Based Clock Optimization Method 2 ProblemsMoving FFs to different regions will drastically increase interconnect delaysHuge performance lossHow do we solve this?
29 Extraction and Verification Design Flow from 1st dayPartitionFront-endphysical designFloorplanningPlacementRoutingBack-endphysical designExtraction and Verification
30 Floorplanning Based Clock Optimization Method 3 Circuit PartitioningConsider Clock and Delay DomainFloorplanningNot Using Embedded Clock ConstraintsEmbedded Clock Constraint ViolationNoYesRegional Clock AssignmentBased on Current FloorplanningDoneIncremental FloorplanningUse Embedded Clock Constraints
31 In Structured ASIC’s Partitioning Floorplanning Create clusters of cells and FFs based on clock, delay, and other constraintsFloorplanningAssigning the clusters to each regionIncremental FloorplanningMove violating FFs to other regions
32 With Partitioning and Floorplanning Less FFs movedLess damage to performanceMethod 1: Number-based heuristicsMethod 2: Placement-based embedded clock optimizationMethod 3: Floorplan-based embedded clock optimization
33 ConclusionsEnhancements should be made to existing EDA tools to achieve a better performance result on structured ASIC architecturesThe structured ASIC is a revolution to businesses, but another evolution of ASIC implementationThe structured ASIC was developed to bridge the gap between the FPGA and the Standard Cell-based ASIC
34 ReferencesT. Okamoto, T. Kimoto, N. Maeda, “Design Methodology and Tools for NEC Electronics - Structured ASIC ISSP", [p. 90] Proceeding of the 2004 international symposium on Physical design.B. Zahiri, “Structured ASICs: Opportunities and Challenges,” Proceedings of the 21st International Conference on Computer Design (ICCD’03).K. Wu, Y. Tsai, “Structured ASIC, Evolution or Revolution?,” Faraday Technology Corporation, Proceedings of the 2004 International Symposium on Physical Design.
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