Download presentation

Presentation is loading. Please wait.

Published byJayce Huckaby Modified over 2 years ago

1
. Copyright 2000 Alternative System Concepts, Inc. asc Floating Point Types for Synthesis Alex N. D. Zamfirescu Alternative System Concepts, Inc. VIUF October, 2000

2
. Copyright 2000 Alternative System Concepts, Inc. asc Presentation Outline qIntroduction qFloating point numbers qVHDL floating point problems qSolutions l IEEE 754 model kind VHDL FP type l Support Java virtual machine FP l Arbitrary FP VHDL types qHow to proceed qVerification speed qConclusion

3
. Copyright 2000 Alternative System Concepts, Inc. asc Introduction (1 of 2) qComputers are integer machines, real numbers are represented using complex codes qThe “IEEE Floating-Point Standard Format” is described in IEEE 754 Std. (best explained in [1]) qTerm “floating-point”) (FP means that there is no fixed number of digits before and after the decimal point (decimal point can float) q For specific algorithms more then necessary computations are performed. Many extra operations have little or no effect

4
. Copyright 2000 Alternative System Concepts, Inc. asc Reality qFP operations are area and power expensive - optimizations are required qSmaller cores do not provide FP support today qMany optimizations are not feasible with a strict standard format (fixed size fields) qHigh precision machines are hard to design using just what the standard IEEE 754 provides (simple, double and extended precision)

5
. Copyright 2000 Alternative System Concepts, Inc. asc Floating Point Numbers (1 of 2) qGeneral form of FP number is x = s * M * B ^p qRepresentations restrict ranges of mantissa M and exponent p, and chose base B qAfter computations some bits of the mantissa are not stored l chopped (completely discarded) l rounded 4 to infinity 4 to zero 4 random

6
. Copyright 2000 Alternative System Concepts, Inc. asc Floating Point Numbers (2 of 2) qStoring 1.11010101 with 3 places after point gives l 1.110 when chopping l 1.111 while rounding qFirst bit after normalization can be hidden (since it is known to be always one) qIEEE std uses B = 2 works from a number written as x = s*1.ffff...ff(binary)*2^p where mantissa is a binary number whose leading 1 will be “hidden when the number is stored qOther issues: NAN, and zero representation and exception handling (underflow, overflow)

7
. Copyright 2000 Alternative System Concepts, Inc. asc VHDL FP Problems qTwo kinds of FP formats are considered l machine kind - formats used by the machines implementing VHDL l model kind - formats used in the model qFirst Problem: Either the machine and the model formats are the same or the model format is not easily recognizable by synthesis tools qSecond Problem: Operations with proprietary model kind FP formats are not fast enough to enable execution and evaluation of different choices

8
. Copyright 2000 Alternative System Concepts, Inc. asc Solution 1: Bit Access to an IEEE 754 Format qSupport IEEE 754 for specific standard bit (std_logic) vector types qMake convention for bit sign qSpecify mantissa size via attribute or convention for specific bit (i.e. bit zero) qCONS: l need smaller less expensive (area and/or power) formats l design of future high precision machines is not addressed l choices needed for zero, NANs and exceptions are arbitrary exponent 0 -m-m mantissa n

9
. Copyright 2000 Alternative System Concepts, Inc. asc Solution 2: Support for Java Virtual Machine FP Type qJava Virtual Machine support for FP is standard qMany hand held devices currently designed have to support Java qAn enhanced solution 1 where all choices for what IEEE 754 left open follow most popular alternatives qSame first two CONS as Solution 1

10
. Copyright 2000 Alternative System Concepts, Inc. asc Solution 3: Arbitrary FP VHDL Types The Challenges (1 of 3) qA relatively complex set of properties has to be specified to characterize the format qOperators have to be specified for all possible combinations of choices qLose synthesis choices have to be left in handling some exceptions qFormat properties should either be associated with the model or be automatically extracted form available library data

11
. Copyright 2000 Alternative System Concepts, Inc. asc Solution 3: Arbitrary FP VHDL Types Describing the type (2 of 3) qVHDL attributes do not provide for l verification that set is complete and values are in a permitted l outside VHDL format (challenge number 4) qSolution: Enter the FP format properties via XML l as a string value of a VHDL attribute, l directly insertion in VHDL (after VHDL language modifications that would permit it) qXML enables checking of any rules that FP formats properties have to comply with qSame XML file could be extracted from libraries and then read by the synthesis and verification tools

12
. Copyright 2000 Alternative System Concepts, Inc. asc Solution 3: Arbitrary FP VHDL Types Describing operators (3 of 3) qThe second challenge could be addressed via the introduction of a minimal set of new VHDL type system features qThe following features will help reduce the difficulty of implementing the operator functionality for all possible choices l “Protected” polymorphism (language can stay strong typed only specific packages get the feature) l Variant records l C++ like templates. In fact (such features are also required in describing configurable hardware)

13
. Copyright 2000 Alternative System Concepts, Inc. asc How to Proceed (1 of 3) Tasks listed by solution qSolution 1 and 2: l agreement on the definition of the type l implementation of a library of operators qSolution 3. l The design of a DTD (document template definition) for the XML content (FP type properties like sizes, normalization, exponent encoding, base value, truncation scheme, hidden bit, exception handling, defaults, etc.) l A choice for the XML insertion mechanism into VHDL l The extension/import of ADA-95 machine kind FP attributes to the model kind VHDL FP types l The implementation of a library of operators after extending the language to support templates.

14
. Copyright 2000 Alternative System Concepts, Inc. asc How to Proceed (2 of 3) Standard development implications qStart as enhancements of IEEE 1076.3 or under IEEE project 1076.6 qXML approach to the type descriptor is sharable (with Verilog, and system level efforts) qTherefore, the type descriptor belongs to a set of standards that are shared by more languages

15
. Copyright 2000 Alternative System Concepts, Inc. asc How to Proceed (3 of 3) Semantics standards and their inheritors XML DTD or Schema What is the content of a FP type descriptor Common HDL definitions (i.e.design hierarchy, event) Future VHDL Verilog FP library implementation Future Verilog VHDL FP library implementation FP Operator semantic

16
. Copyright 2000 Alternative System Concepts, Inc. asc Verification Speed Acceleration feasible via: 1. Resident machine FP - when all model FP parameter ranges are included in the IEEE 754 permitted ranges 2. Byte and word manipulations in C or native code 3. Configurable co-processor - programmable at elaboration - connected over the bus

17
. Copyright 2000 Alternative System Concepts, Inc. asc Conclusion qDistinction between machine and model kind FP types reveals VHDL FP problems qSupporting IEEE 754 Java VM like FP types is the best simple solution qAn XML based FP descriptor could lead to unified support of FP types in VHDL and Verilog qRole for semantic standards in HDL was identified qA new set of optimizations for area and low power become feasible through the users’ choice of FP formats qMeaning (semantics) inheritance is more important then model properties inheritance (for the HDL progress)

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google