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SISSA Trieste AMD and SUN Roberto Dognini Business Development Enterprise Manager Trieste, 22 Novembre 2004.

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Presentation on theme: "SISSA Trieste AMD and SUN Roberto Dognini Business Development Enterprise Manager Trieste, 22 Novembre 2004."— Presentation transcript:

1 SISSA Trieste AMD and SUN Roberto Dognini Business Development Enterprise Manager Trieste, 22 Novembre 2004

2 Trieste 22 Novembre AMD Overview A leading global supplier of innovative semiconductor solutions for the personal and enterprise computing, communications and consumer electronic markets Founded: 1969 Headquarters: Sunnyvale, California Employees: 15,000 worldwide Sales Mix: 80% international 2003 Revenue: $3.5 billion 2004 Q2 Revenue: $1.262 billion Flash Memory: $673 million Microprocessors:$554 million Other: $34 million

3 Trieste 22 Novembre AMD’s Extensive Processor History 8080A Second source microprocessors Am386 Am486 K5™ 2001

4 Trieste 22 Novembre AMD An Innovation Powerhouse AMD 1,090 1, * Technology Patents in 2002 Source: IFI Claims, 2003 Year RankCompany U.S. Patents * 1IBM3,333 2CANON 1,895 3NEC 1,833 3MICRON 1,833 5HITACHI1,616 6MATSUSHITA1,566 7SONY 1,456 8GE1,417 9MITSUBISHI1,408 10SAMSUNG1,329 11FUJITSU1,263 12TOSHIBA1,171 13AMD1,154 14INTEL1,080 15HP1,065 16PHILIPS848 17MOTOROLA TI724 19XEROX701 20FUJI695 Intel

5 Trieste 22 Novembre An industry defining moment. Joining 20 years of enterprise expertise with industry standard economics, targeting the delivery of high performance systems at accessible prices. More Than A Product Announcement

6 Trieste 22 Novembre Building the AMD64 Ecosystem AMD and SUN Key independent software vendors are already embracing the Sun and AMD Opteron processor-based offering as the standard in network computing: BEA Systems, Cadence Design Systems, Inc., Computer Associates, Documentum, MatrixOne Inc., Oracle, Synopsys, Inc., and SAP AG.

7 Trieste 22 Novembre Key Architecture Innovations AMD’s Eighth Generation processor integrates key system elements: Integrated DDR memory controller Next generation core HyperTransport™ technology L2 Cache L1 Instruct. Cache L1 Data Cache X Processor Core HyperTransport™ technology DDR Memory Controller “Hammer” Architecture

8 Trieste 22 Novembre Building a Bridge from the 32- to the 64-bit World Adds 64-bit capabilities to the world’s highest performing 32-bit core for 2P and 4P servers Provides investment protection for users who have invested in 32-bit application software Current 32-bit applications will work on today’s 32-bit operating systems as well as tomorrow’s 64-bit operating systems –Windows XP, Windows 2000 –Windows (with AMD64 compatibility) –Windows Server 2003 –Linux for x86, Linux for AMD64 Enables a gradual application transition to 64-bits as required by end-user individual needs Doesn’t require special hardware or investment in a proprietary infrastructure 32-bit Operating System 64-bit Operating System 32-bit Applications 64-bit Applications

9 Trieste 22 Novembre Intel Xeon Processor-based ServerAMD Opteron™ Processor-based Server IntelXeonProcessorIntelXeonProcessor Memory Ctlr Hub (MCH) 1 Memory Ctlr Hub (MCH) 1 I/O Hub 3 I/O Hub 3 PCI PCI-X IDE, USB, LPC, Etc. PCI-X Bridge 2 PCI-X Bridge 2 I/O & Memory Share FSB Memory Access Delayed By Passing Through MCH Bandwidth Bottlenecks: Link Bandwidth < I/O Bridge Bandwidth More Chips Needed for Basic Server IntelXeonProcessorIntelXeonProcessor DDR 144-bit *AMD-8131™ HyperTransport PCI-X Tunnel **AMD-8111™ HyperTransport I/O Hub AMDOpteron™ProcessorAMDOpteron™Processor PCI-X Bridge* PCI-X Bridge* I/O Hub** I/O Hub** PCI PCI-X IDE, USB, LPC, Etc. DDR 144-bit HyperTransport™ Technology Buses for Glueless I/O or CPU Expansion Separate Memory and I/O Paths Eliminates Most Bus Contention HyperTransport Link Has Ample Bandwidth For I/O Devices Fewer Chips Needed For Basic Server (Reduces Cost) AMDOpteronProcessorAMDOpteronProcessor DDR 144-bit Key Memory Traffic I/O Traffic IPC Traffic Key Memory Traffic I/O Traffic IPC Traffic Architecture Memory Access Technology Primary Bus Technology Memory Capacity Scales w/ Number of Processors Second Processor Competes for FSB Bus Bandwidth AMD Opteron™ Processor-based ServerIntel Xeon Processor-based Server AMD64 Architecture Enables simultaneous high-performance 32- and 64-bit computing Allows businesses to migrate to 64-bit computing as they require IA32 Architecture High-performance 32-bit computing only Businesses needing 64-bit benefits must switch to a new architecture Integrated DDR Memory Controller Dramatically reduces latency for fast memory reads Provides a dedicated path from memory to processor Memory bandwidth scales as processors are added Helps eliminate need for larger caches “Northbridge”-style Memory Controller via Front Side Bus Passage through memory controller hub delays memory reads Processors compete for FSB bandwidth Memory and I/O must share FSB bandwidth, further reducing the efficiency of the FSB HyperTransport™ Technology At up to 6.4 GB/s bandwidth per link, HyperTransport provides sufficient bandwidth for supporting new and existing interconnects including Fibre Channel, Gigabit Ethernet, PCI-X, PCI-X 2.0, Serial-ATA, Serial Attached SCSI and 10G Ethernet Proprietary Hub I/O Buses PCI-X bridge’s 2 hub interface has only half the peak bandwidth of the two PCI-X bridges I/O Hub 3 interface bus can be overloaded by the aggregate demands of its many I/O devices AMD, the AMD Arrow logo, AMD Opteron and combinations thereof, and AMD-8111 and AMD-8131 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product and company names used herein may be trademarks of their respective companies. 1 Intel E7500 Chipset Memory Controller Hub (MCH) 2 Intel 82870P2 64-bit PCI/PCI-X Controller Hub 2 (P64H2) 3 Intel 82801CA I/O Controller Hub 3-S (ICH3-S)

10 Trieste 22 Novembre AMD Opteron Processor-based Server AMD64 Architecture: provides simultaneous high-performance 32-bit and 64-bit computing. Scales to 8P without glue logic. Integrated Memory Controller: provides low-latency memory access and bandwidth that scales as processors are added. HyperTransport Technology: at up to 6.4GB/s bandwidth per link, designed to provide a high-speed connection between processors and core logic with sufficient bandwidth for supporting new and existing interconnects. AMD Opteron™ Processor-based ServerIntel Xeon MP Processor-based Server Key Memory Traffic I/O Traffic IPC Traffic Key Memory Traffic I/O Traffic IPC Traffic HyperTransport™ Technology Buses for Glueless I/O or CPU Expansion HyperTransport™ Technology Buses Enable Glueless Expansion for up to 8-way Servers Separate Memory and I/O Paths Eliminates Most Bus Contention HyperTransport Link Has Ample Bandwidth For I/O Devices Memory Capacity Scales w/ Number of Processors PCI-X Bridge * PCI-X Bridge * PCI-X Other Bridge Other Bridge Other I/OAMD Opteron ™ ProcessorAMD Processor AMDOpteronProcessorAMDOpteronProcessor DDR 144-bit AMDOpteronProcessorAMDOpteronProcessor AMDOpteronProcessorAMDOpteronProcessor DDR 144-bit DDR 144-bit DDR 144-bit PCI-X Bridge PCI-X Bridge I/O Hub** I/O Hub** IDE, USB, LPC, Etc. FSB Bus Bandwidth Shared Across All Four Processors I/O & Memory Share FSB Bandwidth Bottlenecks: Link Bandwidth < I/O Bridge Bandwidth 9-Chip Chipset Needed for 4-way Server IntelXeonProcessorIntelXeonProcessorIntelXeonProcessorIntelXeonProcessor IntelXeonProcessorIntelXeonProcessor IntelXeonProcessorIntelXeonProcessor I/O Hub 3 I/O Hub 3 PCI IDE, FDC, USB, Etc. PCI-X Bridge 2 PCI-X Bridge 2 Memory Ctlr Hub (MCH) 1 Memory Ctlr Hub (MCH) 1 PCI-X Bridge PCI-X Bridge PCI-X Bridge PCI-X Bridge DDR 144-bit Memory Address Buffer 4 Memory Address Buffer 4 Maximum of Four Processors per Memory Controller Hub Maximum of Three PCI-X Bridges per Memory Controller Hub Limited Memory Bandwidth Shared by All Memory AMD, the AMD Arrow logo, AMD Opteron and combinations thereof, and AMD-8111 and AMD-8131 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product and company names used herein may be trademarks of their respective companies. *AMD-8131™ HyperTransport PCI-X Tunnel **AMD-8111™ HyperTransport I/O Hub 1 ServerWorks CMIC HE Memory Controller Hub (MCH) 2 ServerWorks CIOB-X 64-bit PCI/PCI-X Controller Hub 3 ServerWorks CSB5 I/O Controller Hub 4 ServerWorks REMC Memory Address Buffer Intel Xeon MP Processor-based Server IA32 Architecture: provides high-performance 32-bit computing only—does not offer 64-bit benefits. “Northbridge”-based Memory Controller: All four processors compete for fixed memory and front-side bus bandwidths—8P solutions require even more chips. Proprietary Hub I/O Buses: bridge and hub devices can be overwhelmed by the I/O demands of attached peripherals. Memory Address Buffer Memory Address Buffer DDR 144-bit DDR 144-bit Memory Address Buffer Memory Address Buffer Memory Address Buffer Memory Address Buffer DDR 144-bit Fewer Chips Needed for 4-way Server (Reduces Cost)

11 11 Scalable Memory Bandwidth and IO Opteron’s on die IO controller SystemRequestQueue CPU 0 CPU 1 DDR Memory IO HT Link Crossbar CPU-CPU HT Link 6.4GB/s 6.4 GB/s 6.4 – 8.0 GB/s GB/s 6.4 – 8.0 GB/s GB/s 25.6 – 28.8 GB/s 1.6 – 2.0 GT/s coherent 1.6 GT/s non-coherent Dual channels to DDR Memory AMD Opteron™ Processor Server Intel Xeon MP Processor Server Key Memory Traffic I/O Traffic IPC Traffic Key Memory Traffic I/O Traffic IPC Traffic HyperTransport™ Technology Buses for Glueless I/O or CPU Expansion HyperTransport™ Technology Buses Enable Glueless Expansion for up to 8-way Servers Separate Memory and I/O Paths Eliminates Most Bus Contention HyperTransport Link Has Ample Bandwidth For I/O Devices Memory Capacity Scales w/ Number of Processors PCI-X Bridge * PCI-X Bridge * PCI-X Other Bridge Other Bridge Other I/O AMD Opteron™ Processor AMD Opteron™ Processor AMD Opteron Processor AMD Opteron Processor DDR144-bit AMD Opteron Processor AMD Opteron Processor AMD Opteron Processor AMD Opteron Processor PCI-X Bridge PCI-X Bridge I/O Hub** I/O Hub** IDE, USB, LPC, Etc. FSB Bus Bandwidth Shared Across All Four Processors I/O & Memory Share FSB Bandwidth Bottlenecks: Link Bandwidth < I/O Bridge Bandwidth Intel Xeon Processor Intel Xeon Processor Intel Xeon Processor Intel Xeon Processor Intel Xeon Processor Intel Xeon Processor Intel Xeon Processor Intel Xeon Processor I/O Hub 3 I/O Hub 3 PCI IDE, FDC, USB, Etc. PCI-X PCI-X Bridge 2 PCI-X Memory Ctlr Hub (MCH)Memory (MCH) PCI-X PCI-XBridgePCI-XBridge PCI-XBridgePCI-XBridge MemoryAddressBufferMemoryAddressBuffer Maximum of Four Processors per Memory Controller Hub Maximum of Three PCI-X Bridges per Memory Controller Hub Limited Memory Bandwidth Shared by All Memory MemoryAddressBufferMemoryAddressBuffer MemoryAddressBufferMemoryAddressBuffer Memory Address Buffer Memory Address Buffer DDR144-bit 144-bit 144-bit 144-bit 144-bit 144-bit 144-bit 4 Separate IO Channels per CPU – Scalable SMP Bandwidth  4 Separate IO Channels per CPU – Scalable SMP Bandwidth  Hyptertransport TM Interconnect – low SMP memory latency  Commodity/High Performance SMP Solution  presently dual core ready – SRQ controller has port for 2 nd core  fewer # of chips required for MP chipsets – lowering cost of SMP systems 6.4 GB/s XeonEMT GB/s41.6 GB/s12.8 GB/sOpteron 4P2P1PArchitecture > 200 ns~200 ns80 nsXeonEMT 110 ns75 ns50 nsOpteron 4P2P1PArchitecture

12 12 ACML – AMD’s superior equivalent of MKL Compilers – PGI performance enhancements Speed up Opteron Architecture


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