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May 17, 20001 Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips w Peripheral Component - Peter Teng, NEC.

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Presentation on theme: "May 17, 20001 Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips w Peripheral Component - Peter Teng, NEC."— Presentation transcript:

1 May 17, Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips w Peripheral Component - Peter Teng, NEC

2 May 17, Peripheral Design Options - Choosing the Right Partner Peter Teng Engineering Manager Computer Technology I/O Group NEC Electronics Inc.

3 May 17, Path from Discrete to ASIC w Better pricing w Throughput boost w Pinout flexibility w Multi-core integration w Process differences w Target specifications mismatch w Longer design effort and time w Tied to certain ASIC vendors w ASIC NRE charges w Minimum volume requirements AdvantagesDisadvantages

4 May 17, Function ASIC Configuration SIEEPC User Logic Hard Macro 12 MHz Soft Macro USB 1.1 ASIC PHYPHY EPC User Logic Soft Macro 2-chip Solution ASIC/FPGA Standard Product Standard Product USB 2.0 PHYEPC User Logic Hard Macro 480 MHz Soft Macro 1-chip Solution ASIC

5 May 17, USB IDE Bridge Setup USB 2.0/1.X Host Controller/Hub USB 2.0/1.X Host Controller/Hub EPCSpecificClassEPCSpecificClass USB 2.0 USB 2.0 SIE/PHY CPU IF Connector Local Bus Controller(FPGA) Controller(FPGA) 33 MHz 32-bit Bus 33 MHz 32-bit Bus Local Bus Connector USB 2.0 EPC EVA Board 33 MHz 32-bit CPU Bus Ultra DMA 33 CPUV832CPUV832 CPU Board CPU IF Connector IEEE 1284/ UART UART UDMAControllerUDMAController

6 May 17, Evaluation Board Advantages w Hands-on experience w Easy development and performance benchmarking w Early bug detection w Prototype area for system expansion w Platform flexibility meets developers’ requirement

7 May 17, Simulation Environment w Environment of complete models – Host – Hub – Endpoint w USB bus monitors for both 2.0 and 1.1 w Proprietary bus monitors for CPU/DMA/SIE Test scenarios HC model PHY/SIE model USB 2.0 Host Model USB 2.0 Bus Monitor USB 2.0 Hub Model PHY/SIE model USB 2.0 Function SIE USB 2.0 Function SIE PHY/SIE model USB 2.0 Function Macro USB 2.0 Function Macro SIE Monitor DMA/CPU IF CPU/DMAModel/MonitorCPU/DMAModel/Monitor EPC RAM

8 May 17, Hub TT Design Carve up operation Normal receive operation

9 May 17, Simulation Environment Consideration w Represents accurate timing RTL implementation w Offers complete simulation and verification environment w Provides fast host, hub, and function emulation w Performs protocol and compliance checking w Configures to developers’ requirements w Offers sample setup allowing for fast and easy startup

10 May 17, ASIC Vendor Selection w Effortless transition from discrete to ASIC solution w Complete packaging solution – Availability of development platform – Complete simulation environment – Excellent ASIC service w Matching product roadmap w Quality and experience

11 May 17, NEC USB 2.0 Roadmap Storage core Transceiver & SIE ASSP Transceiver Hub ASSP HubController Host ASSP HostController Transceiver & SIE core Transceiver Printer core 2000 Host (RTL) Hub (RTL) FunctionController TransceiverASSPTransceiverASSP USB 2.0 to IDE(UDMA/33) ASSP Mockup USB 2.0 to IDE(UDMA/33) ASSP Mockup USB 2.0 to IDE (UDMA/66) ASSP USB 2.0 to IDE (UDMA/66) ASSP Generic(RTL)Generic(RTL) MarAprMayJunJulAugSepOctNovDec nd ES June 2 nd ES May


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