Presentation is loading. Please wait.

Presentation is loading. Please wait.

© H. Heck 2008Section 1.31 Module 1:Introduction Topic 3:Interconnect Technology OGI EE564 Howard Heck.

Similar presentations


Presentation on theme: "© H. Heck 2008Section 1.31 Module 1:Introduction Topic 3:Interconnect Technology OGI EE564 Howard Heck."— Presentation transcript:

1 © H. Heck 2008Section 1.31 Module 1:Introduction Topic 3:Interconnect Technology OGI EE564 Howard Heck

2 Interconnect Technology EE 564 © H. Heck 2008 Section 1.32 Where Are We? 1.Introduction 1.Overview 2.Trends & Challenges 3.Interconnect Technology 2.Transmission Line Basics 3.Analysis Tools 4.Metrics & Methodology 5.Advanced Transmission Lines 6.Multi-Gb/s Signaling 7.Special Topics

3 Interconnect Technology EE 564 © H. Heck 2008 Section 1.33 Contents Component Packaging Passive Components Connectors Printed Circuit Boards

4 Interconnect Technology EE 564 © H. Heck 2008 Section 1.34 Overview Components (Chip + Pkg) PCB (Motherboard) PCB (add-in card) Connector Source: Intel Corp.

5 Interconnect Technology EE 564 © H. Heck 2008 Section 1.35 Overview – SOA Desktop Motherboard Microprocessor Memory Slots Chipset Graphics Connector

6 Interconnect Technology EE 564 © H. Heck 2008 Section 1.36 Overview – SOA Desktop Motherboard Microprocessor Memory Connectors Chipset Graphics Connector X48 chipset motherboard

7 Interconnect Technology EE 564 © H. Heck 2008 Section 1.37 Component Packaging Packages house the silicon chips. They provide:  Mechanical support  Heat removal  Environmental protection  Electrical signal & power connections (chip to PCB). Silicon Package PCB Soldered Connections Heat Spreader

8 Interconnect Technology EE 564 © H. Heck 2008 Section 1.38 Component Packaging

9 Interconnect Technology EE 564 © H. Heck 2008 Section 1.39 Component Packaging Source: Intel Corp.

10 Interconnect Technology EE 564 © H. Heck 2008 Section 1.310 Example: Flip Chip Pinned Grid Array Bottom Top Cross-section

11 Interconnect Technology EE 564 © H. Heck 2008 Section 1.311 Medium Speed Package Electrical Models Bond WireTracePin / Land Tie Bar L bw R L pin R Z 0,  d R tb, L tb, C tb Die Board Source: Packaging Databook, Intel Corp Today’s speeds demand that we use fully coupled 3D package models.

12 Interconnect Technology EE 564 © H. Heck 2008 Section 1.312 Passive Components Resistors Uses: termination for interconnect, pull up/down for static features Variability: 5%, 2%, 1% Chip resistors – 1 resistor per component R-Packs – up to 4 resistors per small outline component Resistor networks – more resistors per component Lead inductance and package crosstalk can be important effects for high frequency applications. Capacitors Variability: 20%, 10% Chip capacitors – used for high frequency (local) decoupling of power suppliers Tantalum capacitors – used for bulk decoupling At high frequencies, resistance and inductance of the packages must be included in the models.

13 Interconnect Technology EE 564 © H. Heck 2008 Section 1.313 Sockets & Connectors Sockets connect packages to PCBs. Connectors connect PCBs to PCBs. Connection is mechanical between two metal surfaces. LGA775 Socket DIMM connector PCI® Express

14 Interconnect Technology EE 564 © H. Heck 2008 Section 1.314 Socket/Connector Electrical Models These are simple models. Coupled models are frequently used for high performance applications. R con Z 0con,  dcon Today’s speeds demand that we use fully coupled 3D connector models.

15 Interconnect Technology EE 564 © H. Heck 2008 Section 1.315 Printed Circuit Boards Function: provide electrical signal connections between components & deliver power to the components. Material Set: Construction:  Typically 4 to 6 layers (always an even number).  4 layer board: 2 signal, 2 power ($0.09/in 2 )  6 layer board: 4 signal, 2 power ($0.18-$0.24/in 2 )  Higher layer counts are available at higher cost.

16 Interconnect Technology EE 564 © H. Heck 2008 Section 1.316 PCB Construction Power Plane Signal Trace Solder Mask Via Barrel Surface Mount Pad Via Land Laminate (Dielectric) Laminate (Resin) Laminate (Glass) Signal Trace Power Plane Solder Mask

17 Interconnect Technology EE 564 © H. Heck 2008 Section 1.317 PCB Signal Layer 0.050" G 0.005" W  0.024" D 2 0.005" S 1 0.006" S 2  0.012" D 1

18 Interconnect Technology EE 564 © H. Heck 2008 Section 1.318 PCB Vias Vias make layer-layer connections by drilling holes and filling them with conductor material (copper). They are used in chips, package, and boards. Silicon Package PCB Soldered Connections Heat Spreader

19 Interconnect Technology EE 564 © H. Heck 2008 Section 1.319 PCB Design Goals Function: All signals connected Performance: Maximum operating frequency Cost  Minimized technology requirements Layer count Board size Relaxed width & spacing Relaxed via size  Design for manufacturability Component selection Component placement Trade routing

20 Interconnect Technology EE 564 © H. Heck 2008 Section 1.320 Summary Package electrical parameters are typically modeled with lumped circuit elements and transmission lines. We will examine the effects of lumped elements later, and will account for them in our design project. We will also consider when transmission line models are required. For high volume PCs, system designers use pervasive, low cost PCB solutions:  FR-4 material set  4 layer boards  5/5 or 6/6 mil trace/space wiring  4 boards per panel for motherboards PCBs are used for motherboards, add-in cards, and CPU packages. PCBs provide interconnect for high speed buses operating as high as 400 MHz/800 MT/s and beyond.

21 Interconnect Technology EE 564 © H. Heck 2008 Section 1.321 References Intel Packaging Databook, Intel Corporation, 2002, http://developer.intel.com/design/packtech/packbook.htm. Component Types Used for SMT, IBM Microelectronics Division, January 1994. Surface Mount Design and Land Pattern Standard, IPC-SM-782, IPC, Revision A – August 1993. R.R. Tummala, E.J. Rymaszewski (ed.), Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989.

22 Interconnect Technology EE 564 © H. Heck 2008 Section 1.322 Appendix: More Packages Celeron® Processor Package Celeron® Processor Cartridge Pentium® Processor w/ MMX™ Package 850 Chipset Package

23 Interconnect Technology EE 564 © H. Heck 2008 Section 1.323 Appendix: More Connectors ISA PCI Memory DIMM SLOT1 AGP

24 Interconnect Technology EE 564 © H. Heck 2008 Section 1.324 Appendix: CPU Sockets PGA370


Download ppt "© H. Heck 2008Section 1.31 Module 1:Introduction Topic 3:Interconnect Technology OGI EE564 Howard Heck."

Similar presentations


Ads by Google