Presentation on theme: "Polyphase FIR Filter Implementation for Communication Systems"— Presentation transcript:
1 Polyphase FIR Filter Implementation for Communication Systems DSP C5000Chapter 20Polyphase FIR Filter Implementation for Communication Systems
2 Multirate Processing 1 of 2 Multirate processing arises in many fields of digital signal processing:Digital audio: sampling frequency conversion (32 kHz, 44.1kHz, 48kHz), sharp cut-off of FIR filter, …Signal processing for digital communications: symbol rate processing, bit rate processing, sample rate processing, …Speech processing: 3G speech codec (Adaptive Multi Rate), fractionnal pitch estimation, ...…3G = Third generation of cellular mobile communications.
3 Multirate Processing 2 of 2 Involves two actions on the digital signal:Downsampling: resampling downwards the digital signal in the digital domain.Upsampling: resampling upwards the digital signal in the digital domain.MFeFe/MRetain one sample over M and discardthe M-1 others, every M samples.LFeLFeDownsampling decreases the sampling rate by discarding samples (decimation).Upsampling adds extra samples (interpolation).Insert L-1 zeros between each sample
5 Downsampling 2 of 2 Anti-aliasing Filter Noble identity for decimation x(n)y(m)H(z)FeFe/Mfc : (Fe/M)/2The anti-aliasing filter removes frequences above the Nyquist frequency for the new sampling rate.MH(zM)MH(z)
7 Upsampling 2 of 2 Interpolating Filter Noble identity for upsampling L x(m)y(n)H(z)LFeFefC : (Fe/L)/2The interpolating filter smoothes out the values that were filled with zeroes.Interpolating filter with unity gain have an Equivalent noise bandwidth of 1/L so it cancels 1/Lth of the signal energy. Thus it needs to have a gain of L to preserve the signal magnitude after interpolation.H(zL)LH(z)L
8 Polyphase Implementation of FIR Filters Decimation Case 1 of 4 H(z)ME(zM)Let n=lM+kwith
9 Polyphase Implementation of FIR Filters Decimation Case 2 of 4 TimeProcessing load (MAC/s)MTeNMH(z)ME0(zM)E1(zM)EM-1(zM)z-1FeFe/MM-1 filter evaluation over Mare discarded.N filter length
10 Polyphase Implementation of FIR Filters Decimation Case 3 of 4 Using noble identityME0(z)E1(z)EM-1(z)z-1FeFe/MTimeProcessing load (MAC/s)MTeNNo more useless computations, but one sampling period over M, CPU is burdned with N MAC/s.
11 Polyphase Implementation of FIR Filters Decimation Case 4 of 4 Equivalent commutator modelE0(z)Processing load (MAC/s)E1(z)N/MEM-1(z)MTeTimeFeFe/MCommutator runs at Fe,. At each input sample only one component is computed and accu-mulated with the result of the previous one. The result is output when the last componentis reached and accumulator is reset. This spreads the processing load over MTe.
12 Polyphase Implementation of FIR Filters Interpolation Case 1 of 5 H(z)R(zL)LLet n=mL+L-1-kwith
13 Polyphase Implementation of FIR Filters Interpolation Case 2 of 5 H(z)Processing load (MAC/s)NR0(zL)R1(zL)RM-1(zL)z-1LTe/LTimeL-1 multiplications by 0 over LFor each filter evaluation.N filter length.FeLFe
14 Polyphase Implementation of FIR Filters Interpolation Case 3 of 5 Using noble identityR0(z)R1(z)RM-1(z)LAt each output sampling instant,only one component is non zeroz-1LLFeLFe
15 Polyphase Implementation of FIR Filters Interpolation Case 4 of 5 Equivalent commutator modelR0(z)R1(z)RM-1(z)Processing load (MAC/s)N/LTe/LTimeFeLFeFor each output sampling instant one polyphase component is computed.When we reach again the first component (M-1) a new input sample is inputedin the delay line of each polyphase component.
16 Polyphase Implementation of FIR Filters Interpolation Case 5 of 5 Linear Periodically Varying Time systemz-1z-1hL-1h2L-1h3L-1z-1h0h1hL-1hLhL+1h2L-1h2L+1h3L-1h2Lz-1z-1h1hL+1h2L+1h0z-1hLh2L
17 Case Study Shaping filters for a QPSK modem : Emitter: interpolation case.Receiver: decimation caseEfficient Algorithm Implementation :Good ordering of computations,Efficient memory organization and management.
18 Emitter 1 of 4 QPSK modulator Fb Fs Fe fk s(t)=1/2[cos(2pfot).cos(f(Ak,Bk))-sin(2pfot).sin(f(Ak,Bk))]QPSK modulatorCos()RCFDACAkfkfk: PhasecomputationbitsBkSin()RCFDACFbFsFeRCF: raised cosine filterDAC: digital to analog converterBitfrequencySymbolfrequencySamplefrequency
19 Emitter 2 of 4 Let Fe=16Fs (16 sample / symbol) Define a raised cosine filter with:6 symbols length.Roll_off : 0.5Matlab commandh=RCOSFIR(0.5,3,16,1);Equivalent system16H(z)In red: ideal interpolating filterIn blue: actual RC filter
20 Emitter 3 of 4 The 16 Polyphase filters are defined by : Filter length is 97, impulse response is padded with 0 to reach 112=7*16With N=112 and L=16
21 Emitter 4 of 4 Shuffle coefficients Coefficients Symbols 1st sample R=flipud(reshape(h,8,12));R=round(R*2^15);fid=fopen('coef.inc','wt');for p=1:8fprintf(fid,'\t.word\t%d\n,R(p,:))endfclose(fid);2nd sample15th sampleWhen coefficient pointer reaches this address a newsymbol will be input at the next output sample period
23 _firTxQ:… ;context save LD #var,DPSTM #coefsize,BKMVDM adbufQ,AR2 ;current coefs pointerSTM #1,AR0STM #filbufQ,AR3 ;symbol bufferSTL A,*AR3 ;new sample (guess hold during 16 samples)RPTZ A,#Lfil-1 ;compute one polyphase componentMAC *AR2+0%,*AR3+,AMVMD AR2,adbufQ ;save new current coefs pointerSFTA A,-16SFTA A,-1 ;output of RCF can be greater than 1 !;test if delay symbols is neededBC endTxQ,NTC ;jump if not necessaryMAR *+AR3(-2)RPT #Lfil-2DELAY *AR3-endTxQ:… ;context restoreRET
24 Symbol vs Sample Output Symbol outputSample outputFe: 16 khzFs: 1 khzDf : p/4 constant for each symbolf= Fs/8=125 Hz
25 Receiver 1 of 2 Fe Fb Fs Bit processing Symbol processing ADC RCF ADC
26 Receiver 2 of 2 Receiver structure is quite similar, except that: Each polyphase component has its own delay tapEach polyphase output has to be accumulated for M polyphase computations and accumulator is outputed every M input sample and reset.E0(z)E1(z)EM-1(z)
27 Follow on Activities Laboratory 10 for the TMS320C5416 DSK Illustrates the effects of decimation and anti-aliasing filters.Laboratory 11 for the TMS320C5416 DSKIllustrates the effects of interpolation and anti-imaging filters.Application 9 for the TMS320C5416 DSKUses interpolation and decimation to produce sharper cut-offs FIRs than would be obtained otherwise.
28 ReferenceDigital Signal Processing a Practical Approach by Emmanuel C. Ifeachor and Barrie W. Jervis. Chapter 9. Multirate digital signal processing.
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