1. Polyphase FIR Filter Implementation for Communication Systems
DSP C5000
Chapter 20
Polyphase FIR Filter Implementation for Communication Systems

2. Multirate Processing 1 of 2
Multirate processing arises in many fields of digital signal processing:
Digital audio: sampling frequency conversion (32 kHz, 44.1kHz, 48kHz), sharp cut-off of FIR filter, …
Signal processing for digital communications: symbol rate processing, bit rate processing, sample rate processing, …
Speech processing: 3G speech codec (Adaptive Multi Rate), fractionnal pitch estimation, ... …
3G = Third generation of cellular mobile communications.

3. Multirate Processing 2 of 2
Involves two actions on the digital signal:
Downsampling: resampling downwards the digital signal in the digital domain.
Upsampling: resampling upwards the digital signal in the digital domain. M Fe
Fe/M
Retain one sample over M and discard
the M-1 others, every M samples. L Fe
LFe
Downsampling decreases the sampling rate by discarding samples (decimation).
Upsampling adds extra samples (interpolation).
Insert L-1 zeros between each sample

4. Downsampling 1 of 2 M
x(n)
y(m)
Folding term

5. Downsampling 2 of 2 Anti-aliasing Filter Noble identity for decimation
x(n)
y(m)
H(z) Fe
Fe/M
fc : (Fe/M)/2
The anti-aliasing filter removes frequences above the Nyquist frequency for the new sampling rate. M
H(zM) M
H(z)

6. Upsampling 1 of 2
x(m)
y(n) L

7. Upsampling 2 of 2 Interpolating Filter Noble identity for upsampling L
x(m)
y(n)
H(z)
LFe Fe
fC : (Fe/L)/2
The interpolating filter smoothes out the values that were filled with zeroes.
Interpolating filter with unity gain have an Equivalent noise bandwidth of 1/L so it cancels 1/Lth of the signal energy. Thus it needs to have a gain of L to preserve the signal magnitude after interpolation.
H(zL) L
H(z) L

8. Polyphase Implementation of FIR Filters Decimation Case 1 of 4
H(z) M
E(zM)
Let n=lM+k
with

9. Polyphase Implementation of FIR Filters Decimation Case 2 of 4
Time
Processing load (MAC/s)
MTe N M
H(z) M
E0(zM)
E1(zM)
EM-1(zM)
z-1 Fe
Fe/M
M-1 filter evaluation over M
are discarded.
N filter length

10. Polyphase Implementation of FIR Filters Decimation Case 3 of 4
Using noble identity M
E0(z)
E1(z)
EM-1(z)
z-1 Fe
Fe/M
Time
Processing load (MAC/s)
MTe N
No more useless computations, but one sampling period over M, CPU is burdned with N MAC/s.

11. Polyphase Implementation of FIR Filters Decimation Case 4 of 4
Equivalent commutator model
E0(z)
Processing load (MAC/s)
E1(z)
N/M
EM-1(z)
MTe
Time Fe
Fe/M
Commutator runs at Fe,. At each input sample only one component is computed and accu-
mulated with the result of the previous one. The result is output when the last component
is reached and accumulator is reset. This spreads the processing load over MTe.

12. Polyphase Implementation of FIR Filters Interpolation Case 1 of 5
H(z)
R(zL) L
Let n=mL+L-1-k
with

13. Polyphase Implementation of FIR Filters Interpolation Case 2 of 5
H(z)
Processing load (MAC/s) N
R0(zL)
R1(zL)
RM-1(zL)
z-1 L
Te/L
Time
L-1 multiplications by 0 over L
For each filter evaluation.
N filter length. Fe
LFe

14. Polyphase Implementation of FIR Filters Interpolation Case 3 of 5
Using noble identity
R0(z)
R1(z)
RM-1(z) L
At each output sampling instant,
only one component is non zero
z-1 L L Fe
LFe

15. Polyphase Implementation of FIR Filters Interpolation Case 4 of 5
Equivalent commutator model
R0(z)
R1(z)
RM-1(z)
Processing load (MAC/s)
N/L
Te/L
Time Fe
LFe
For each output sampling instant one polyphase component is computed.
When we reach again the first component (M-1) a new input sample is inputed
in the delay line of each polyphase component.

16. Polyphase Implementation of FIR Filters Interpolation Case 5 of 5
Linear Periodically Varying Time system
z-1
z-1
hL-1
h2L-1
h3L-1
z-1 h0 h1
hL-1 hL
hL+1
h2L-1
h2L+1
h3L-1
h2L
z-1
z-1 h1
hL+1
h2L+1 h0
z-1 hL
h2L

17. Case Study Shaping filters for a QPSK modem :
Emitter: interpolation case.
Receiver: decimation case
Efficient Algorithm Implementation :
Good ordering of computations,
Efficient memory organization and management.

18. Emitter 1 of 4 QPSK modulator Fb Fs Fe fk
s(t)=1/2[cos(2pfot).cos(f(Ak,Bk))-sin(2pfot).sin(f(Ak,Bk))]
QPSK modulator
Cos()
RCF
DAC Ak fk
fk: Phase
computation
bits Bk
Sin()
RCF
DAC Fb Fs Fe
RCF: raised cosine filter
DAC: digital to analog converter
Bit
frequency
Symbol
frequency
Sample
frequency

19. Emitter 2 of 4 Let Fe=16Fs (16 sample / symbol)
Define a raised cosine filter with:
6 symbols length.
Roll_off : 0.5
Matlab command
h=RCOSFIR(0.5,3,16,1);
Equivalent system 16
H(z)
In red: ideal interpolating filter
In blue: actual RC filter

20. Emitter 3 of 4 The 16 Polyphase filters are defined by :
Filter length is 97, impulse response is padded with 0 to reach 112=7*16
With N=112 and L=16

21. Emitter 4 of 4 Shuffle coefficients Coefficients Symbols 1st sample
R=flipud(reshape(h,8,12));
R=round(R*2^15);
fid=fopen('coef.inc','wt');
for p=1:8
fprintf(fid,'\t.word\t%d\n,R(p,:))
end
fclose(fid);
2nd sample
15th sample
When coefficient pointer reaches this address a new
symbol will be input at the next output sample period

22. Emitter (C callable) .sect "coefs2"
Ncomp .set 16 ;number of polyphase component
coefs2 .include "coefpoly2.inc"
coefsfin:
coefsize .set coefsfin-coefs2
Lfil .set coefsize/Ncomp ;polyphase component length
filbufQ .usect "filtre2",Lfil ;data buffer
.text
_firinit:
ST #coefs2,*(adbufQ) ;pointer to current coefs pointer
STM #filbufQ,AR2 ;zeroed initial buffer condition
RPT #Lfil-1
STL A,*AR2+
RET

23. _firTxQ:… ;context save
LD #var,DP
STM #coefsize,BK
MVDM adbufQ,AR2 ;current coefs pointer
STM #1,AR0
STM #filbufQ,AR3 ;symbol buffer
STL A,*AR3 ;new sample (guess hold during 16 samples)
RPTZ A,#Lfil-1 ;compute one polyphase component
MAC *AR2+0%,*AR3+,A
MVMD AR2,adbufQ ;save new current coefs pointer
SFTA A,-16
SFTA A,-1 ;output of RCF can be greater than 1 !
;test if delay symbols is needed
BC endTxQ,NTC ;jump if not necessary
MAR *+AR3(-2)
RPT #Lfil-2
DELAY *AR3-
endTxQ:
… ;context restore
RET

24. Symbol vs Sample Output
Symbol output
Sample output
Fe: 16 khz
Fs: 1 khz
Df : p/4 constant for each symbol
f= Fs/8=125 Hz

25. Receiver 1 of 2 Fe Fb Fs Bit processing Symbol processing ADC RCF ADC

26. Receiver 2 of 2 Receiver structure is quite similar, except that:
Each polyphase component has its own delay tap
Each polyphase output has to be accumulated for M polyphase computations and accumulator is outputed every M input sample and reset.
E0(z)
E1(z)
EM-1(z)

27. Follow on Activities Laboratory 10 for the TMS320C5416 DSK
Illustrates the effects of decimation and anti-aliasing filters.
Laboratory 11 for the TMS320C5416 DSK
Illustrates the effects of interpolation and anti-imaging filters.
Application 9 for the TMS320C5416 DSK
Uses interpolation and decimation to produce sharper cut-offs FIRs than would be obtained otherwise.

28. Reference
Digital Signal Processing a Practical Approach by Emmanuel C. Ifeachor and Barrie W. Jervis. Chapter 9. Multirate digital signal processing.