1. Spring 2003 1 CS-EE 481 University of Portland School of Engineering Project Bushtit 01/28/03 Project Bushtit An Interface between Radio Telemetry and Wireless Communication February Review Joseph Madson Chun-Chang Chiu Jonathan Clark Sara Sundborg

2. Spring 2003 2 CS-EE 481 Project Bushtit 01/28/03 University of Portland School of Engineering Overview Review of Project Accomplishments –Option 1 Code Completed –Interrupt Programming Completed –Received Microcontroller parts and book Plans Issues Milestones Conclusion

3. Spring 2003 3 CS-EE 481 University of Portland School of Engineering Project Bushtit 01/28/03 Bushtit Interface PIC18F452 Microcontroller EM5R RS-232 Interface Chip ROM Communications ROM HQ Decagon Inc. RM1 23B On/off 1 1 2 3 R B Block Diagram: Hardware Description

4. Spring 2003 4 CS-EE 481 Project Bushtit 01/28/03 University of Portland School of Engineering Accomplishments TOPs V1.0 Approved Option 1 Completed Computer Connected to Internet Part Received –PIC18F452 Microcontroller –Two 3M ACE board Model 327 –3M Breadboard Jumper Wire Kit –Microchip ICD Module –Ten Panasonic Red Clear T-1 3.0 LED –Microcontroller Book Design Implementation Completed –Initial Interrupt Programming –Memory Allocation Scheme

5. Spring 2003 5 CS-EE 481 Project Bushtit 01/28/03 University of Portland School of Engineering Block Diagram: Interrupt Priorities Initial Main loop Int 1 Int 2 Int 3 Receive Transmit Options/Error Checking/DSP Battery Error Checking In/Out Block Diagram: Memory Allocation 1 1 1 1 0 Bytes 45 Bytes DSP ASCII signal (RM1) Non-ASCII numbers Delete above memory block at first non- ASCII memory location

6. Spring 2003 6 CS-EE 481 Project Bushtit 01/28/03 University of Portland School of Engineering Plans Start Debugging PIC18F542 Subroutine Implementation –Debug Memory Allocation –Debug Interrupt Priorities –Finish Option 2 & 3 –Finish Error Checking

7. Spring 2003 7 CS-EE 481 Project Bushtit 01/28/03 University of Portland School of Engineering Issues Reorder Demonstration Kit for the Microcontroller PIC18F542 Finish Debugging Testing with ROM equipment questionable

8. Spring 2003 8 CS-EE 481 Project Bushtit 01/28/03 University of Portland School of Engineering Milestones

9. Spring 2003 9 CS-EE 481 Project Bushtit 01/28/03 University of Portland School of Engineering Conclusions Received All Parts except Demonstration Kit Finished Option 1 Finished Interrupt (debug) Finished Memory Allocation (debug)